Efficient circuit clustering for area and power reduction in FPGAs

Abstract-In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original Odin [1] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. Odin II also interfaces directly with VPR [2], a common academic FPGA CAD flow, allowing an architectural description of a target FPGA as an input to enable identification and mapping of design features to custom features. Furthermore, Odin II can also read the netlists from downstream CAD stages into its netlist data-structure to facilitate analysis. Odin II can be used for a wide range of experiments; in this paper, we show three specific instances of how Odin II can be used by ASIC and FPGA researchers for more than basic synthesis. Odin II is open source and released under the MIT License.

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“…The basic programmable cell of an FPGA is a Basic Logic Elements (BLEs), which itself is commonly a combination of a LUT and flip-flop [12].…”

Section: A Fpga Cad Flowmentioning

confidence: 99%

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Jamieson

Kent

Gharibian

et al. 2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

130

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“…Power-driven Timing-driven Routability-driven P-T-VPack, [18] SMAC, [12] SCPlace, [10] T-VPack, [4] T-RPack, [9] HDPack, [13] Marrakchi et al [11] * Target less than max logic utilization: "depopulated" CLBs Uniform depopulation * Non-uniform depopulation * T-NDPack Un/DoPack, [3] Tom and Lemieux [7] iRac, [5] Tessier and Giza [6] Figure 1: Categorization of clustering techniques based on logic utilization approach and optimization goals.…”

Section: Clustering Techniquesmentioning

confidence: 99%

“…Additionally, total area increases by 5%, along with 7% increase in critical path delay. All depopulation-based clustering algorithms [3,5,6] increase critical path delay, while enhancing the routability.…”

Section: Clustering Techniquesmentioning

confidence: 99%

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Timing-Driven Nonuniform Depopulation-Based Clustering

Liu

Akoglu

2010

International Journal of Reconfigurable Computing

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the lowcost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulationbased clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

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“…This is especially the case for FPGA designs because a larger amount of transistors have to be provided in the wiring channels and logic blocks to provide programmability for signal transition. Studies show that interconnects alone contribute 70-80% of the total area [2] and 75-85% of the total power [3] [4] for most of the FPGA designs.…”

Section: Introductionmentioning

confidence: 99%

Register binding and port assignment for multiplexer optimization

Chen¹,

Cong²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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-Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. In this paper, we first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After technology mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.

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Efficient circuit clustering for area and power reduction in FPGAs

Cited by 93 publications

References 24 publications

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Timing-Driven Nonuniform Depopulation-Based Clustering

Register binding and port assignment for multiplexer optimization

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