Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits

Ebrahimi, Seyyed Ashkan; Reshadinezhad, Mohammad Reza; Bohlooli, Ali; Shahsavari, Mahyar

doi:10.1016/j.mejo.2016.04.016

Cited by 67 publications

(53 citation statements)

References 29 publications

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“…As it is obvious in Figure A, the chirality vector ( m, n ), determines the angle of Carbon atoms along the structure, which can be considered as: armchair ( m, m ), zigzag ( m, 0 ), and chiral for other ( m, n ) values. Therefore, if k is assumed to be an integer number, m–n = 3 k defines the conducting behavior for the SWCNT structure, while m–n ≠ 3 k defines the semiconducting behavior for the CNT structure . Therefore, assuming the lattice constant is defined as a = 2.49 Å, the diameter of a CNT structure ( D CNT ) can be expressed as follows :

D_{CNT} = \frac{a \sqrt{m^{2} + n^{2} + italicmn}}{π}

…”

Section: Cntfet Technologymentioning

confidence: 99%

“…Therefore, if k is assumed to be an integer number, m-n = 3 k defines the conducting behavior for the SWCNT structure, while m-n 6 ¼ 3 k defines the semiconducting behavior for the CNT structure. [18][19][20] Therefore, assuming the lattice constant is defined as a = 2.49 Å, the diameter of a CNT structure (D CNT ) can be expressed as follows 16,17,[19][20][21] : Figure 1B shows the physical structure of a sample CNTFET in which the semiconducting doped nanotubes are considered as the channel region, which is controlled by V GS , similar to a typical MOSFET device. 22 The threshold voltage (V T ) of the CNTFET can be approximately expressed as Equation (2), where q is the electric charge of an electron, and V π = 3.033 eV is the carbon π-π bond energy.…”

Section: Cntfet Technologymentioning

confidence: 99%

“…[15][16][17] Therefore, carbon nanotube field-effect transistor (CNTFET) with MOSFET-like behavior is a promising candidate for replacing the CMOS technology. [16][17][18][19][20][21] Some of the advantages of CNTFETs are: higher mobility of carriers due to the quasi-ballistic transfer, small chip size, lower intrinsic delay due to lower parasitic capacitances, better (g m /I D ) characteristics versus normalized drain current…”

Section: Introductionmentioning

confidence: 99%

“…Giving the above facts, CNTFETs are widely used in the design of digital integrated circuits such as full adders and multiplexers. [19][20][21] Therefore, design of analog integrated circuits such as active filters in the CNTFET technology still demands much scientific effort. 16,17 The main objective of this article is to present a new universal and mixed-mode filter that can be used as input/middle stage in the target applications such as radio-frequency identification (RFID), analog FM broadcasting, and over the horizon (OTH) radar systems.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A CNTFET universal mixed‐mode biquad active filter in subthreshold region

Zanjani

Dousti

Dolatshahi

2018

Int J RF Microw Comput Aided Eng

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This paper presents a new low‐voltage and low‐power mixed‐mode universal active filter, using only 12 carbon nanotube field effect transistors (CNTFETs) and 2 grounded capacitors to improve the noise performance of the proposed circuit. Due to the use of subthreshold transistors biased at ±0.2 V supply voltage, the power consumption of the proposed multi input‐single output (MISO) filter is only 850 nW at 19 MHz center frequency. On the other hand, relaxing from any matching components, the center frequency and quality factor of the proposed filter can be tuned electronically with low sensitivity to the values of the active and passive elements. Furthermore, the active chip area of the proposed filter is significantly reduced to 0.047 μm2, in 32 nm CNTFET technology. Therefore, as the HSPICE simulation results show, the input referred noise values at 19 MHz are reduced to 15.5 nV/Hz and 185 fA/Hz in voltage and current modes, respectively. It is also shown that, by changing the number of nanotubes in the CNTFET structure, a very good power‐frequency trade‐off can be achieved for low‐power GHz applications.

show abstract

D_{CNT} = \frac{a \sqrt{m^{2} + n^{2} + italicmn}}{π}

…”

Section: Cntfet Technologymentioning

confidence: 99%

Section: Cntfet Technologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A CNTFET universal mixed‐mode biquad active filter in subthreshold region

Zanjani

Dousti

Dolatshahi

2018

Int J RF Microw Comput Aided Eng

View full text Add to dashboard Cite

show abstract

“…For instance, the changes in the count of the intended invertors, transistors and consecutive gates, the size of transistors and simplification of wirings, affect the speed, delay, power consumption and circuit size. It is possible to apply one or a combination of several logics in full-adder implementation for any arithmetic circuit [2,3].…”

Section: Introductionmentioning

confidence: 99%

Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology

Nejadzadeh¹,

Reshadinezhad²

2018

IJMECS

Self Cite

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In this article a new design of a current mode full-adder is proposed through the field effect transistors based on carbon nanotubes. The outperformance of the current mode full-adder constructed by CNTFET compared to that of constructed by CMOS is observable in the simulation and comparisons. This circuit operates based on triple input majority function. The simulation is run by HSPICE software according to the model proposed in Stanford University for CNTFETs at 0.65 V power supply voltage. The proposed circuit outperforms compared to the previous current mode full-adders in terms of speed, accuracy and PDP.

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Design and Simulation of Innovative QCA Quaternary Logic Gates

Akbari‐Hasanjani

Sabbaghi‐Nadooshan

2021

Advcd Theory and Sims

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This paper proposes a new cell configuration for quaternary Quantum Cellular Automata (QQCA) based on the calculation of polarization. The proposed QQCA cell is based on a three-particle system that creates instability within a cell in the gate design. Therefore, a single-particle system or binary QCA (bQCA) technology and a two-particle system or Ternary QCA (TQCA) technology have been used to implement quaternary logic. The proposed cell can be implemented in two layers or in one, using input and output drives. According to the dimensions of the proposed model for QQCA and simulation of basic gates, designing with this cell is quite optimal; it requires five cells in the design of the AND and OR gates and two cells in the design of the NOT gate. Based on the number of cells used in the basic gates, the total area in the AND and OR gates is 576 × 10 −6 µm 2 and in the NOT gate is 276 × 10 −6 µm 2 . The base gates are fully optimized and latency is equal to 0.25 clockcycle or 0.25 × 10 −12 s, which is reduced in comparison with prior works. Also, the power consumption of a cell in terms of quantum calculation and the proposed model is also investigated.

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Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits

Cited by 67 publications

References 29 publications

A CNTFET universal mixed‐mode biquad active filter in subthreshold region

A CNTFET universal mixed‐mode biquad active filter in subthreshold region

Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology

Design and Simulation of Innovative QCA Quaternary Logic Gates

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