Efficient custom instruction generation based on characterizing of basic blocks

Liang, Guoqiang; Ma, Yuchun; Zhao, Kang; Bian, Jinian

doi:10.1109/cscwd.2013.6580946

Cited by 2 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 4 Framework of Custom instruction For validating our strategy, we use benchmark of Trimaran and gain CI candidates by using identification algorithm in [5] as inputs to strategy. Then output estimation results to CI generation as a selection criteria.…”

Section: Resultsmentioning

confidence: 99%

“…Performance enhancement is estimated by measuring reduction of execution cycle. Based on characterizing of basic blocks to explore CI candidates, Liang proposed an efficient custom instruction generation algorithm in [5]. Meanwhile Liang adopted CDFG (Control Data Flow Graph) as IR.…”

Section: Fig1 Data-path Of CI Candidatesmentioning

confidence: 99%

“…1a and Fig. 1b depicted have the equal area value for area cost model in [5], because they have same operations and interconnections. But they need different number (1 and 2) of LEs (Logic Elements) to implement their function.…”

Section: Fig1 Data-path Of CI Candidatesmentioning

confidence: 99%

See 2 more Smart Citations

A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

Liu

2014

AMR

View full text Add to dashboard Cite

Area cost estimation model is important for accurate measurement of area on reconfigurable processor. However, in the process of CI (Custom Instruction), traditional model can’t accurately estimate area cost of CI candidates. In the paper, we propose a novel strategy of area cost estimation. According to island-style FPGA (Field Programmable Gate Array) structure, the strategy firstly enumerated all BCs (Basic Cells) from data-path of CI candidates. Then checked all the validity of BCs enumerated, and selected the unique BC set to overlap original data-paths. We lastly used the effective estimation model based on BC to accurately measure area cost of candidates. Experimental results show that novel strategy can accurately estimate area cost of CI candidates, which is very close to actual result from a HLS (High Level Synthesis) tool, and deviation is less than 6%.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Fig1 Data-path Of CI Candidatesmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

Liu

2014

AMR

View full text Add to dashboard Cite

show abstract

“…We selected a unique set of valid BCs to overlap original DFGs of CI candidates by using a heuristic algorithm of graph overlapping in [5] (e.g. BC 1 and BC 2 in Figure 3c).…”

Section: Bc Overlappingmentioning

confidence: 99%

“…Based on characterizing of basic blocks to explore CI candidates, Liang proposed an efficient custom instruction generation algorithm in [5] [6].…”

Section: Introductionmentioning

confidence: 99%

An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

Liu¹,

Ma²,

Wu³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

View full text Add to dashboard Cite

Abstract-Area reduction is very important for CI (Custom Instruction) on reconfigurable processor. However, for FPGA (Field Programmable Gate Array) structure, resource sharing method is inefficient for area reduction of data-path. In the paper, we propose an effective strategy of area reduction for custom instruction. Firstly, we partitioned data-path of the final CI to lots of BCs (Basic Cells). Then we checked all the validity of BCs to make sure that each BC can be realized using single logic element of FPGA, and selected the unique BC set to overlap original data-paths. Finally, on the basis of BC partitioning, we adopt an approach of Merging CIs to reduce area cost of data-path, which is different from traditional method of resource sharing. Experiment results show that basic cell can really represent FPGA architecture, compared to a method of efficient resource sharing, the approach of merging CIs based on BC can lead to more than 11% average reduction of area.

show abstract

Efficient custom instruction generation based on characterizing of basic blocks

Cited by 2 publications

References 7 publications

A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

Contact Info

Product

Resources

About