Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

Shi, C.-J.R.; Tian, M.W.; Shi, Guoyong

doi:10.1109/tcad.2005.855884

Cited by 18 publications

(10 citation statements)

References 16 publications

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“…The runs are unrelated, i.e., every fault transient run simulates the entire time interval without any reuse of the knowledge obtained from the golden and previous fault runs. One ingredient of our fast fault simulation is the reuse of the already obtained simulation data, especially from the golden run (see also Shi et al, 2006), where this was applied for DC fault simulation). Topological differences between a fault and the golden circuit description are minor and local (one resistor of difference only).…”

Section: Simultaneous Fault Simulationmentioning

confidence: 99%

“…At a particular time point we can reuse generated matrices and even their decomposed versions for all circuit models whose signals do not differ much from the golden run. We can apply the Sherman-Morrison-Woodbury formula (Householder, 1957) to update the inverse matrix, which improves the efficiency of the solver (Shi et al, 2006). Ideally, if a particular fault result is almost the same as the golden run, we could obtain the solution almost instantly (almost no additional efforts are required).…”

Section: Simultaneous Fault Simulationmentioning

confidence: 99%

See 1 more Smart Citation

Robust DC and efficient time-domain fast fault simulation

Tasic

Dohmen

Maten

et al. 2014

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -Imperfactions in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the effciency of these simulations. Design/methodology/approach -Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and efficient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. Finding -We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation. Originality/value -Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very efficient.

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Section: Simultaneous Fault Simulationmentioning

confidence: 99%

Section: Simultaneous Fault Simulationmentioning

confidence: 99%

Robust DC and efficient time-domain fast fault simulation

Tasic

Dohmen

Maten

et al. 2014

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

View full text Add to dashboard Cite

show abstract

“…In this method, a circuit netlist is abstracted to a gate-level or a RTL (Register-TransferLevel) model, and faults are injected structurally at the abstract model. The advantage of this approach is that it can predict faulty behaviors effectively using a structural fault model [9]. However, as explained in the previous section, the defect-based fault simulation of analog circuits requires long simulation time due to the difficulty in abstracting the fault model to higher level.…”

Section: Previous Workmentioning

confidence: 99%

“…To resolve this issue, there have been various studies to reduce the analog fault simulation time by reducing the complexity of the simulation algorithm. In [9], the authors present the method to speed up the DC fault simulation time of nonlinear analog circuits by reducing the complexity of Newton-Raphson iteration and fault ordering. Recently, Liu et al [2] proposed an hierarchical process variability analysis technique with information reuse to reduce the time required to perform fault simulation and test selection.…”

Section: Previous Workmentioning

confidence: 99%

Defect-based analog fault coverage analysis using mixed-mode fault simulation

Parky

Madhavapeddiz

Paglieri

et al. 2009

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop

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A fault coverage analysis has become an important tool to evaluate the testability of developing circuits and to come up with an effective test plan. However, the fault coverage analysis of analog circuits has not gained much attention due to the long fault simulation time and the absence of widely accepted fault models. This paper presents an efficient framework for the analog fault coverage analysis to provide repeatable and predictable analog test metrics. The presented method uses a defectbased analysis method in which faults are modeled at a transistor-level to examine faulty behavior in a structural way. In order to conduct the defect-based fault simulation in a manageable time, we develop a mixed-mode fault simulation flow which uses both behavioral-level HDL (Hardware Description Language) model and transistorlevel SPICE model simultaneously. Also, the information of transistor geometry is used in the analysis to reflect the different defect probabilities of transistors of various sizes. Our method was applied to a full-chip level fault analysis of a commercial mixed-signal IP, and the analysis result shows a good correlation with an actual post-silicon test data.

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“…It uses March algorithms with a ( 2 ) complexity. Was proposed Simulation Fault methods, like Distributed Fault Simulation [14], z-Diagnostic [15], Dynamic Fault Clustering [16], One-Step Relaxation and Adaptive Simulation Continuation [17]. All these simulation programs require prior knowledge of hardware description languages such HDL, proprietary scripts or C code to develop their functions.…”

Section: Introductionmentioning

confidence: 99%

SET and SEU simulation toolkit for LabVIEW

Bartra

Reis

2011

2011 12th European Conference on Radiation and Its Effects on Components and Systems

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Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults of any process step is essential to ensure that the design is well implemented. During the simulation various problems can be detected and corrected. It is presented a tool to simulate the effects that occur when a source of fault is inserted in a digital circuit, especially SEU faults. To model a fault, it was also developed a TMR method capable of verifying the existence of a fault and to not let it spread through the whole circuit. It was also developed a Voltage Controlled Oscillator (VCO) to view fault effects in analog circuits. LabVIEW tool is used to create a set of virtual instruments to simulate SEUs. It is efficient in modeling the Characteristics of SETs. It is possible with this toolkit to replicate the effects of SEUs and SETs described in the literature.

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Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

Cited by 18 publications

References 16 publications

Robust DC and efficient time-domain fast fault simulation

Robust DC and efficient time-domain fast fault simulation

Defect-based analog fault coverage analysis using mixed-mode fault simulation

SET and SEU simulation toolkit for LabVIEW

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