Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

Abstract

In this paper, we present a regular partial product array (PPA) for radix-8 Booth multiplication by removing the extra row with a small overhead complexity. A radix-8 multiplier design is proposed based on the regular PPA which offers a saving of 10.7 % area-delay product (ADP) over the existing radix-8 multiplier design. The n lower-order bits of 2n bit output of full-width multiplier are truncated to have a fixed-width multiplier with low truncation error, where n is the operand bit-width. Few redundant logic operations are created in the adder unit when n lower-order bits of 2n-bit multiplier output are truncated. A specific design is necessary as the modern synthesis tools partially remove these redundant logics. We present an optimized adder unit design after removing redundant logic for post-truncated fixed-width radix-8 Booth multiplier. Comparison result shows that the proposed post-truncated fixedwidth multiplier design offers nearly 20.7 % ADP and 18.3 % power saving over the existing radix-8 design optimized by the Synopsys Design Compiler when 2n-bit output is post-truncated to n-bit. More often, multipliers are used for multiplication of constant. The value of the constant may be fixed or could be changed during runtime by the user. The multiplier that multiplies fixed constant is referred to fixedconstant multiplier and that multiplies constant which changes during run-time is referred to generic-constant multiplier. Both radix-4 and radix-8 Booth multiplier designs easily can be configured for a generic-constant multiplier. However, radix-8 multiplier design offers to save some area and delay when configured for constant multiplication, while the radix-4 multiplier design does not have this feature. We find B Abhishek Choubey Circuits Syst Signal Process that the proposed 12-bit full-width and fixed-width radix-8 generic-constant multiplier designs, respectively, involve 19.4 and 24.7 % less ADP than the existing radix-4 fullwidth and post-truncated multiplier designs configured for constant multiplication. The existing block-based lifting 2-D DWT structure is synthesized using the proposed radix-8 generic-constant fixed-width multiplier design to demonstrate the effectiveness of proposed multiplier designs. We find that the existing lifting 2-D DWT structure of block size 16 and word length 12 offers 19.3 % ADP saving and 11.5 % power saving when the constant multipliers are implemented using the proposed radix-8 multiplier design instead of the existing radix-4 multiplier design.

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture

“…Design of the proposed work is done using Verilog HDL and the synthesis results are done in Cadence Genus of 90nm technology. The ASIC implementation results of proposed Radix8 Booth multiplier, CSD multiplier and Booth multiplier [16] are shown in Table 4 which shows parameters like delay, area and power. The ADP of the CSD architecture is 29.018% excess ADP (EADP) and for booth multiplier it is 28.22% EADP than proposed Booth multiplier and the PDP of the CSD architecture is 26.12% excess PDP (EPDP) and in booth multiplier it is 34.97% EPDP than proposed architecture are computed and it shows how much better performances does the proposed method gives than the existed method relating to area and power.…”

“…The total number of hardware components used in the 2D DWT is shown in Table 3. Below table comprises of the total number of registers, XOR/XNOR, AND/OR/NOR/NAND gates and latency required for the implementation of the 2DDWT architecture for CSD implementation, Booth multiplier [16] and proposed architecture. The CSD implementation consumes more number of registers and the proposed architecture requires less number of registers.…”

Design of ALU based on Majority Logic for Low Power Applications

“…Default are the remaining parameters). The architectures for multipliers based on 8-bit MLAC 4 and the recent roughly CMOS (45nm) [25] are not directly comparable with the plurality logic b.…”

A Block based Area-Delay Efficient Architecture for Multi-Level Lifting 2-D DWT

“…Unlike RPA-based designs, folded design involves simple control circuitry and it has 100 % HUE. Keeping this in view, several architectures based have been proposed for efficient implementation of lifting 2-D DWT [5][6][7][8][9][10][11][12]. Most of the designs differ by their number of arithmetic components, on-chip memory, cycle period and throughput rate.…”

“…Low-pass block a (9,8) a (10,8) a (11,8) a (12,8) a (13,8) a (14,8) a (15,8) h (4,4) h (4,5) h (4,7) h (4,8) l (4,5) l (4,6) l (4,7) l (4,8) …”