Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

Sutter, Gustavo; Deschamps, Jean-Pierre; Imaña, José Luis

doi:10.1109/tie.2012.2186104

Cited by 140 publications

(114 citation statements)

References 22 publications

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“…For Virtex5, the best reported performance result over GF (2 163 ) is 5.48 µs and is presented in [13] with 6150 slices. Our proposed ECC processor consumes only 4393 slices to compute a point multiplication in 4.91 µs is better in both speed (10%) and area (29%) than that in [13].…”

Section: Implementation Resultsmentioning

confidence: 99%

“…If the field squaring and field addition operations can be operated concurrently with multiplication then the point operations latency will be equivalent to the latency of the six field multiplications. The six multiplications can, for example, be computed in two steps using three multipliers or in three steps using two multipliers or in six steps by serial multiplications using one multiplier [17], [13] and [10]. Again, the digit size can affect the performance of ECC; for example, a bit serial implementation takes m cycles, a digit ( bits) serial one takes ( / ) cycles and a bit parallel implementation takes a single clock cycle [8], [12] and [11].…”

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

“…Many high performance ECC processor implementations on FPGA have been reported in the literature; the most relevant are presented in [10], [11], [12], [13], [14], [15], [16], [17], [20], [21], [22], and [23]. The common optimizing technique of high speed designs is the reduction of latency (number of clock Z. U.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a novel high speed ECC processor implementation for point multiplication on Field Programmable Gate Array (FPGA) is proposed. A new segmented pipelined fullprecision multiplier is used to reduce the latency and the LopezDahab (LD) Montgomery point multiplication algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles required. The proposed ECC architecture has been implemented on Xilinx FPGAs Virtex4, Virtex5 and Virtex7 families. To our knowledge, our single multiplier and three multipliers based designs show the fastest performance to date when compared to reported works individually. Our one multiplier based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the more advanced Virtex7, (3.18 µs at 352 MHz). Finally, the proposed three multiplier based ECC implementation is the first work reporting the lowest number of clock cycles and the fastest ECC processor design on FPGA (450 clock cycles to get 2.83 µs on Virtex7).

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Section: Implementation Resultsmentioning

confidence: 99%

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

See 1 more Smart Citation

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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show abstract

“…Table 3 gives a comparison results with the state-of-the-art implementations. As it is shown in the table below, the implementation in [26] presents a minimal area compared to the proposed ECC architecture while requiring an important execution time at the same time. Thus, the implementation results of the proposed ECC architecture outperform those of the implementation in [28] in terms of area and required time to compute the scalar multiplication.…”

Section: Simulation and Synthesis Results Of Ecc Ipmentioning

confidence: 99%

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

et al. 2017

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Abstract:The Elliptic Curve Digital Signature Algorithm (ECDSA) is the analog to the Digital Signature Algorithm (DSA). Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curves with the 163-bit key length recommended by the NIST (National Institute of Standards and Technology). It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip) and Random Number Generator IP (RNG IP). Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm 2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW). Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks.

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“…Hardware-based implementations of such algorithms have proved to be more efficient than equivalent software's programs in terms of speed and resources usage. This is mainly due to exploring new design architectures [7][8][9][10][11][12]. Such designs are generally written in hardware description languages (HDLs).…”

Section: Introductionmentioning

confidence: 99%

Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Alimi¹,

Lahbib²,

Machhout³

et al. 2017

IJECE

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Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer's functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability. Keyword:Assertion-based verification Co-simulation Cryptography Hardware description language High-level verification Large-integer Matlab/Simulink

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Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

Cited by 140 publications

References 22 publications

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

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