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Algorithms for performing divisions over Z p and GF(p m ) are described, the corresponding digital circuits are synthesized and conclusions about their computation times are drawn. The results of their implementation within field-programmable devices are given in the case of the most efficient ones.

Modular exponentiation with large modulus and exponent, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems. Typically, the Montgomery's modular-multiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. In this paper, we optimize the Montgomery's multiplication and propose architectures to perform the least significant bit first and the most significant bit first algorithms. The developed architecture has the following distinctive characteristics: 1) use of digit serial approach for Montgomery multiplication. 2) Conversion of the CSA representation of intermediate multiplication using carry-skip addition. This allows the critical path to be reduced, albeit with a small-area speed penalty; and 3) precompute the quotient value in Montgomery's iteration in order to speed up the operating frequency. In this paper, we present results in Xilinx Virtex 5 and in 0.18-μm application-specified integrated circuit technologies. For fair comparison with previous works, Xilinx Virtex 2 results are reported. Experimental results show that the proposed modular exponentiation and modular-multiplication design obtain the best delay performance compared with the published works and outperform them in terms of area-time complexity as well.Index Terms-Carry-save addition (CSA), carry-skip addition, modular exponentiation, Montgomery modular multiplication, Rivest-Shamir-Adleman (RSA) cryptosystem, very large scale integration architecture.

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