2014 9th International Design and Test Symposium (IDT) 2014
DOI: 10.1109/idt.2014.7038583
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Efficient embedded SoC hardware/software codesign using virtual platform

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Cited by 6 publications
(3 citation statements)
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“…The "Programmers' View" (PV) level of abstraction consists of the register accurate transaction-level models (TLMs) of the peripherals and the instruction-set simulator (ISS) of the CPU [76]. The fundamental element of the TLM modeling approach is the distinction between the communication layer, functionality, and architectural elements as represented by time and power [77], [78].…”
Section: A Modeling and Simulationmentioning
confidence: 99%
“…The "Programmers' View" (PV) level of abstraction consists of the register accurate transaction-level models (TLMs) of the peripherals and the instruction-set simulator (ISS) of the CPU [76]. The fundamental element of the TLM modeling approach is the distinction between the communication layer, functionality, and architectural elements as represented by time and power [77], [78].…”
Section: A Modeling and Simulationmentioning
confidence: 99%
“…Virtual Platforms (VPs) are emerging as the key technology to build virtual prototyping for real products [6,7,8]. VPs enable fast architecture exploration, early Software (SW) development, and efficient performance analysis.…”
Section: System Level Verification Using Virtual Platformsmentioning
confidence: 99%
“…El concepto de prototipado virtual se presenta como una metodología para la validación temprana de segmentación hardware-software [22]. Se ha propuesto una plataforma virtual para el diseño y simulación de sistemas embebidos en Linux [36].…”
Section: Herramientas Y Algoritmosunclassified