Efficient error detection in Double Error Correction BCH codes for memory applications

Reviriego, Pedro; Argyrides, Costas; Maestro, Juan Antonio

doi:10.1016/j.microrel.2012.01.017

Cited by 27 publications

(15 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…(3) With x is modulate subcarrier k with frequency and is the modulation symbol applied to subcarrier (k) during the interval to the OFDM. Modulation symbols can be BPSK, QPSK, 16QAM or 64QAM [11]. Two orthogonal subcarriers OFDM and are presented in equation (4).…”

Section: Orthogonal Frequency Division Multiplexing (Ofdm)mentioning

confidence: 99%

See 1 more Smart Citation

An Implementation of Error Minimization Data Transmission in OFDM using Modified Convolutional Code

Briantoro

Astawa

Sudarsono

2016

emitter

View full text Add to dashboard Cite

This paper presents about error minimization in OFDM system. In conventional system, usually using channel coding such as BCH Code or Convolutional Code. But, performance BCH Code or Convolutional Code is not good in implementation of OFDM System. Error bits of OFDM system without channel coding is 5.77%. Then, we used convolutional code with code rate 1/2, it can reduce error bitsonly up to 3.85%. So, we proposed OFDM system with Modified Convolutional Code. In this implementation, we used Software Define Radio (SDR), namely Universal Software Radio Peripheral (USRP) NI 2920 as the transmitter and receiver. The result of OFDM system using Modified Convolutional Code with code rate is able recover all character received so can decrease until 0% error bit. Increasing performance of Modified Convolutional Code is about 1 dB in BER of 10 -4 from BCH Code and Convolutional Code. So, performance of Modified Convolutional better than BCH Code or Convolutional Code.

show abstract

Section: Orthogonal Frequency Division Multiplexing (Ofdm)mentioning

confidence: 99%

“…Thus obtained codeword c which corresponds to a polynomial . c(x)=x n−k m(x)+u(x) [10] [11]. Then, first codeword is encoded using default Convolutional Code algorithm.…”

Section: Proposed Modified Convolutional Codementioning

confidence: 99%

An Implementation of Error Minimization Data Transmission in OFDM using Modified Convolutional Code

Briantoro

Astawa

Sudarsono

2016

emitter

View full text Add to dashboard Cite

show abstract

“…They implemented binary BCH codes for 5 bit error correction with a length of 127 bits using Peterson decoding procedure. Author shown that burst error correcting codes are less speed and more complex in hardware compared to BCH codes Application of BCH codes in authentication of binary document images is discussed in [9]. They used (7, 4) BCH encoder for encoding of a character and embedded in a binary document image, each 4 bit in a character is encoded to a 7 bit.…”

Section: Related Workmentioning

confidence: 99%

Fpga Implementation of (15,7) BCH Encoder and Decoder for Text Message

Rohith¹

2013

IJRET

View full text Add to dashboard Cite

show abstract

“…A number of papers proposed to improve the decoding efficiency for multi-bit error correcting codes by distinguishing between single-bit errors and multi-bit errors. In [9], the authors proposed to partially compute the syndromes for doubleerror-correcting BCH codes to detect errors before conducting the error correcting algorithm. In [10], the authors proposed to correct single-bit errors using BCH codes by comparing syndromes to columns of the parity check matrix and correct multi-bit errors using classical decoding methodology for BCH codes.…”

Section: Introductionmentioning

confidence: 99%

“…Compared to works presented in [9], [10], [11], the primary contributions of the paper are two-fold. First, we improved the single-error-correcting stage of the code.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical decoding of double error correcting codes for high speed reliable memories

Wang¹

2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

As the technology moves into the nano-realm, traditional single-error-correcting, double-error-detecting (SEC-DED) codes are no longer sufficient for protecting memories against transient errors due to the increased multi-bit error rate. The well known double-errorcorrecting BCH codes and the classical decoding method for BCH codes based on Berlekamp-Massey algorithm and Chien search cannot be directly adopted to replace SEC-DED codes because of their much larger decoding latency. In this paper, we propose the hierarchical double-errorcorrecting (HDEC) code. The construction methods and the decoder architecture for the codes are described. The presented error correcting algorithm takes only 1 clock cycle to finish if no error or a single-bit error occurs. When there are multi-bit errors, the decoding latency is O(log 2 m) clock cycles for codes defined over GF (2 m ). This is much smaller than the latency for decoding BCH codes using Berlekamp Massey algorithm and Chien search, which is O(k) clock cycles -k is the number of information bits for the code and m ∼ O(log 2 k). Synthesis results show that the proposed (79, 64) HDEC code requires only 80% of the area and consumes < 70% of the power compared to the classical (78, 64) BCH code. For a large bit distortion rate (10 −3 ∼ 10 −2 ), the average decoding latency for the (79, 64) HDEC code is only 36% ∼ 60% of the latency for decoding the (78, 64) BCH code.

show abstract

Efficient error detection in Double Error Correction BCH codes for memory applications

Cited by 27 publications

References 7 publications

An Implementation of Error Minimization Data Transmission in OFDM using Modified Convolutional Code

An Implementation of Error Minimization Data Transmission in OFDM using Modified Convolutional Code

Fpga Implementation of (15,7) BCH Encoder and Decoder for Text Message

Hierarchical decoding of double error correcting codes for high speed reliable memories

Contact Info

Product

Resources

About