Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE

Figueiredo, Felipe Augusto Pereira de; Mathilde, Fabiano; Cardoso, Fabbryccio A. C. M.; Vilela, Rafael M.; Miranda, Joao Paulo

doi:10.1109/reconfig.2014.7032513

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…Firstly, consider the two-channel residue vectors {x 1 i , x 2 i } and {x 1 j , x 2 j }, their mapping results are X i and X j respectively. If mapping results by using (5) are equal, then…”

Section: Optimization For Crtmentioning

confidence: 99%

“…Methods based on linear or non-linear feedback shift registers, congruential and chaotic mapping are common approaches to generating pseudo-random sequence. The pseudo-random code is not only the basis of multiple access of spread spectrum communication system but also the key of synchronization in 4G mobile communication systems [1]. Feedback shift register has a simple and efficient implementation architecture [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…However, it only has small amount of polynomials and has been widely studied. Thus, it is not an appropriate choice in security communication or encryption systems [1,[4][5][6][7]. In the past few decades, pseudo-random sequence generation method based on chaotic mapping has been deeply studied.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A pseudo-random sequence generation scheme based on RNS and permutation polynomials

Liu

Yang

et al. 2018

Sci. China Inf. Sci.

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Long period pseudo-random sequence plays an important role in modern information processing systems. Base on residue number system (RNS) and permutation polynomials over finite fields, a pseudorandom sequence generation scheme is proposed in this paper. It extends several short period random sequences to a long period pseudo-random sequence by using RNS. The short period random sequences are generated parallel by the iterations of permutation polynomials over finite fields. Due to the small dynamic range of each iterative calculation, the bit width in hardware implementation is reduced. As a result, we can use full look-up table (LUT) architecture to achieve high-speed sequence output. The methods to find proper permutation polynomials to generate long period sequences and the optimization algorithm of Chinese remainder theorem (CRT) mapping are also proposed in this paper. The period of generated pseudorandom sequence can exceed 2 100 easily based on common used field programmable gate array (FPGA) chips. Meanwhile, this scheme has extensive freedom in choosing permutation polynomials. For example, 10905 permutation polynomials meet the long period requirement over the finite field Fq with q ≡ 1(mod 3) and q 503. The hardware implementation architecture is simple and multiplier free. Using Xilinx XC7020 FPGA chip, we implement a sequence generator with the period over 2 50 , which only costs 20 18kb-BRAMs (block RAM) and a small amount of logics. And the speed can reach 449.236 Mbps. The National Institute of Standards and Technology (NIST) test results show that the sequence has good random properties.

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Section: Optimization For Crtmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A pseudo-random sequence generation scheme based on RNS and permutation polynomials

Liu

Yang

et al. 2018

Sci. China Inf. Sci.

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“…In LTE and LTE-A, uplink physical random access channel (PRACH) is used for initial access requests from the user equipment (UE) to the evolved base station (eNodeB) and to obtain time synchronisation [3,4]. In case of a need to access the network, a UE requests access by transmitting a random access (RA) preamble through PRACH [5]. The RA preamble is then detected by the PRACH receiver at eNodeB side, which estimates both the ID of the transmitted preamble and the propagation delay between UE and eNodeB.…”

Section: Introductionmentioning

confidence: 99%

An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems

Figueiredo¹,

Cardoso²

2020

Field Programmable Gate Arrays (FPGAs) II

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The Physical Random Access Channel plays an important role in LTE and LTE-A systems. Through this channel, the user equipment aligns its uplink transmissions to the eNodeB's uplink and gains access to the network. One of the initial operations executed by the receiver at eNodeB side is the translation of the channel's signal back to base-band. This operation is a necessary step for preamble detection and can be executed through a time-domain frequency-shift operation. Therefore, in this paper, we present the hardware architecture and design details of an optimised and configurable FPGA-based time-domain frequency shifter. The proposed architecture is based on a customised Numerically Controlled Oscillator that is employed for creating complex exponential samples using only plain logical resources. The main advantage of the proposed architecture is that it completely removes the necessity of saving in memory a huge number of long complex exponentials by making use of a Look-Up Table and exploiting the quarter-wave symmetry of the basis waveform. The results demonstrate that the proposed architecture provides high Spurious Free Dynamic Range signals employing only a minimal number of FPGA resources. Additionally, the proposed architecture presents spur-suppression ranging from 62.13 to 153.58 dB without employing any correction.

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“…In LTE and LTE-A, uplink physical random access channel (PRACH) is used for initial access requests from the user equipment (UE) to the evolved base station (eNodeB) and to obtain time synchronization [3], [4]. In case of need to access the network, a UE requests access by transmitting a random access (RA) preamble through PRACH [5]. The RA preamble is then detected by the PRACH receiver at eNodeB side, which estimates both the ID of the transmitted preamble and the propagation delay between UE and eNodeB.…”

Section: Introductionmentioning

confidence: 99%

An Efficient FPGA-based Frequency Shifter for LTE/LTE-A Systems

Figueiredo¹

2019

Preprint

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The Physical Random Access Channel (PRACH) plays an important role in LTE and LTE-A systems. It is through the PRACH channel that the user equipment (UE), based on eNodeB's timing estimates, aligns its uplink transmissions to the eNodeB's uplink and gain access to the network. One of the initial operations executed by the PRACH receiver at eNodeB side is the translation of the PRACH signal back to base band, $i.e.$, center the PRACH signal around DC. This operation is a necessary step for preamble detection and can be carried out through a time-domain frequency shift operation. Therefore, in this paper we present the hardware architecture and implementation details of a configurable and optimized FPGA-based time-domain frequency shifter. It is a hardware-efficient and accurate architecture for converting the relevant received PRACH signal into base band before further signal processing. The architecture is manly based on a customized Numerically Controlled Oscillator (NCO), which is used for generating complex exponentials employing only adders, a Look-Up Table (LUT) and plain logic resources. The main advantage of the proposed hardware architecture is that it completely eliminates the need for storing a large number of long complex exponential sequences by employing a single LUT and exploiting quarter wave symmetry of the basis waveform. Our simulation results show that the proposed customized NCO architecture provides high Spurious Free Dynamic Range (SFDR) signals using a minimal amount of FPGA resources. Moreover, the proposed architecture exhibits spur-suppression ranging from 62.13 to 153.58 dB without using Taylor Series correction.

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Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE

Cited by 5 publications

References 8 publications

A pseudo-random sequence generation scheme based on RNS and permutation polynomials

A pseudo-random sequence generation scheme based on RNS and permutation polynomials

An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems

An Efficient FPGA-based Frequency Shifter for LTE/LTE-A Systems

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