Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding

Huang, Kuan-Ying; Juang, Jyh‐Ching; Tsai, Yung Fu; Lin, Chun-Ting

doi:10.3390/s21144634

Cited by 7 publications

(6 citation statements)

References 31 publications

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“…More recently, various publications have proposed SoC-FPGA-based designs for specific applications, combining the massive parallelism and energy efficiency of FPGAs with the flexibility of the embedded processors [48][49][50]. In these cases, the most computationally demanding operations are off-loaded to the FPGA, while the SoC processor is mainly dedicated to compute the GNSS basic measurements and navigation solutions: an SoC-FPGA-based receiver is tested to acquire and track GPS L1 C/A satellites in [48], using recorded signals.…”

Section: Literature Reviewmentioning

confidence: 99%

“…In these cases, the most computationally demanding operations are off-loaded to the FPGA, while the SoC processor is mainly dedicated to compute the GNSS basic measurements and navigation solutions: an SoC-FPGA-based receiver is tested to acquire and track GPS L1 C/A satellites in [48], using recorded signals. A dual-frequency receiver is proposed in [49] to test a direct aid to track the GPS L2 and L5 bands after acquiring the L1 C/A signals. Finally, a receiver for reflectometry applications is proposed in [50].…”

Section: Literature Reviewmentioning

confidence: 99%

See 1 more Smart Citation

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

Majoral,

Fernández-Prades,

Arribas

2023

Sensors

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Global navigation satellite system (GNSS) technology is evolving at a rapid pace. The rapid advancement demands rapid prototyping tools to conduct research on new and innovative signals and systems. However, researchers need to deal with the increasing complexity and integration level of GNSS integrated circuits (IC), resulting in limited access to modify or inspect any internal aspect of the receiver. To address these limitations, the authors designed a low-cost System-on-Chip Field-Programmable Gate Array (SoC-FPGA) architecture for prototyping experimental GNSS receivers. The proposed architecture combines the flexibility of software-defined radio (SDR) techniques and the energy efficiency of FPGAs, enabling the development of compact, portable, multi-channel, multi-constellation GNSS receivers for testing novel and non-standard GNSS features with live signals. This paper presents the proposed architecture and design methodology, reviewing the practical application of a spaceborne GNSS receiver and a GNSS rebroadcaster, and introducing the design and initial performance evaluation of a general purpose GNSS receiver serving as a testbed for future research. The receiver is tested, demonstrating the ability of the receiver to acquire and track GNSS signals using static and low Earth orbit (LEO)-scenarios, assessing the observables’ quality and the accuracy of the navigation solutions.

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Section: Literature Reviewmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

Majoral,

Fernández-Prades,

Arribas

2023

Sensors

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show abstract

“…Since Apple proposed OpenCL for heterogeneous computing in 2008, research on using FPGA-based hardware platforms and ARM+FPGA heterogeneous approaches to accelerate CNNs has become increasingly rich [ 25 ]. However, many challenges still exist.…”

Section: Related Workmentioning

confidence: 99%

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence

Liang,

Tan,

Xie

et al. 2023

Sensors

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In recent years, edge intelligence (EI) has emerged, combining edge computing with AI, and specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed high-level synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%. This study provides two different optimization schemes for edge intelligence applications through design and experimentation and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

show abstract

“…Since Apple proposed OpenCL for heterogeneous computing in 2008, research on using FPGAbased hardware platforms and ARM+FPGA heterogeneous approaches to accelerate CNN has become increasingly rich [21]. However, many challenges still exist.…”

Section: Related Workmentioning

confidence: 99%

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence

Liang,

Tan,

Xie

et al. 2023

Preprint

View full text Add to dashboard Cite

In recent years, Edge Intelligence (EI) has emerged, combining edge computing with AI, specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed High-Level Synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%.This study provides two different optimization schemes for edge intelligence applications through design and experimentation, and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

show abstract

Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding

Cited by 7 publications

References 31 publications

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence

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