Efficient FPGA Implementation of an ANN-Based Demapper Using Cross-Layer Analysis

Abstract

In the field of communication, autoencoder (AE) refers to a system that replaces parts of the traditional transmitter and receiver with artificial neural networks (ANNs). To meet the system performance requirements, it is necessary for the AE to adapt to the changing wireless-channel conditions at runtime. Thus, online fine-tuning in the form of ANN-retraining is of great importance. Many algorithms on the ANN layer are developed to improve the AE’s performance at the communication layer. Yet, the link of the system performance and the ANN topology to the hardware layer is not fully explored. In this paper, we analyze the relations between the design layers and present a hardware implementation of an AE-based demapper that enables fine-tuning to adapt to varying channel conditions. As a platform, we selected field-programmable gate arrays (FPGAs) which provide high flexibility and allow to satisfy the low-power and low-latency requirements of embedded communication systems. Furthermore, our cross-layer approach leverages the flexibility of FPGAs to dynamically adapt the degree of parallelism (DOP) to satisfy the system-level requirements and to ensure environmental adaptation. Our solution achieves 2000× higher throughput than a high-performance graphics processor unit (GPU), draws 5× less power than an embedded central processing unit (CPU) and is 5800× more energy efficient compared to an embedded GPU for small batch size. To the best of our knowledge, such a cross-layer design approach combined with FPGA implementation is unprecedented.

Improving Hardware in LUT-Based Mealy FSMs

“…These solutions are very popular at present for the implementation of various projects. This fact is confirmed by the analysis of the literature [22][23][24][25][26][27][28].…”

FPGA-based Trainable Autoencoder for Communication Systems

“…FPGA training accelerators targeting communication systems were presented by Ney et al in 2022 [6] and 2023 [10]. In [6], a trainable NN-based demapper was implemented using a cross-layer-design methodology, and in [10] a novel unsupervised equalizer was presented featuring a fully-pipelined hardware architecture to balance the lifetime of feature maps. However, none of the works is able to satisfy high throughput requirements surpassing 10 Gbit•s −1 .…”

“…In summary, some works focus on accelerating the throughput and processing time of NN training on FPGA [13]- [15]. Other works address low-power and low-energy processing for accelerating the training at the edge [6], [10], [16], [17]. However, there is a clear lack of research focusing on highthroughput inference combined with resource-efficient training on FPGA which is mandatory for our application to satisfy the high-throughput constraints while providing the required adaptability.…”

“…The goal of next-generation communication systems is not only to increase throughput, lower latency, and improve reliability, but also to enhance autonomy by exploiting artificial neural network (ANN)-based communication algorithms [1], which allow for adaptation to varying channel conditions. Although such algorithms often enhance the communication performance of traditional approaches [2]- [4], the adaptation to changing conditions is based on a huge amount of data, required to perform supervised training of the ANN. This training data needs to be transmitted as pilot symbols, lowering the net throughput and information rate of the communication system.…”

“…algorithms [4]- [6]. Especially the equalizer, responsible for mitigating the impairments of the communication channel to increase the reliability of the system, is a component that can benefit from the latest advancements of NN research.…”