Efficient Function Approximation Using Truncated Multipliers and Squarers

Walters, E. George; Schulte, Michael

doi:10.1109/arith.2005.18

Cited by 47 publications

(34 citation statements)

References 13 publications

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“…One method to reduce the hardware needed to accurately approximate elementary functions using polynomials is to use truncated multipliers and squarers within the hardware [26,27]. Unfortunately, incorporating truncated arithmetic units into the architecture complicates the error analysis.…”

Section: Cubic Interpolator Coefficientsmentioning

confidence: 99%

“…A '1' is added to the column immediately to the right of the rounding point, then the k least significant bits at the output are discarded. Figure 2 shows the block diagram of a linear interpolator, where x m is used to select coefficients a 0 and a 1 from a lookup table [26,27]. Multiplier #1 computes a 1 · x l , which is then added to a 0 to produce the output.…”

Section: Finite Precision Arithmetic Effectsmentioning

confidence: 99%

“…With the approach presented in this paper, Chebyshev series approximations are used to select the initial coefficient values for each subinterval [26,27]. First, the number of subintervals, 2 m , is determined.…”

Section: Polynomial Function Approximationmentioning

confidence: 99%

“…Truncated multiplication and squaring units can be used to reduce the area, delay, and power requirements. However, the error associated with the reduced hardware complicates the error analysis required to ensure accurate evaluation of functions [26,27]. This paper presents an optimization method to localize and find a closed-form solution for interpolators that allows for smaller architectures to be realized.…”

Section: Introductionmentioning

confidence: 99%

“…In-between methods can be subdivided into linear approximations [12,24] and quadratic interpolation methods [22,23,[25][26][27] based on the degree of the polynomial approximation employed. The intermediate size of the lookup tables makes them suitable for IEEE single-precision computations (24-bit significand), attaining fast execution with reasonable hardware requirements.…”

Section: Introductionmentioning

confidence: 99%

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Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimizes coefficient lengths to reduce lookup table requirements, maximizes the number of truncated columns to reduce the area, delay and power of the arithmetic units, and minimizes the maximum absolute error of the interpolator output. The method can be used to design interpolators to approximate any function to a user-specified accuracy, up to and beyond 53-bits of precision (e.g., IEEE double precision significand). Linear, quadratic and cubic interpolator designs that approximate reciprocal, square root, reciprocal square root and sine are presented and analyzed. Area, delay and power estimates are given for 16, 24 and 32-bit interpolators that compute the reciprocal function, targeting a 65 nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes compared to previously proposed methods. The method can be used to optimize coefficients in other systems while accounting for coefficient quantization as well as truncation and rounding effects of multiple arithmetic units.

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Section: Cubic Interpolator Coefficientsmentioning

confidence: 99%

Section: Finite Precision Arithmetic Effectsmentioning

confidence: 99%

Section: Polynomial Function Approximationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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Design and Implementation of an Error‐Margin Aware Approach for Non‐Uniform Segmentation of Elementary Functions Using Degree‐N Polynomial Approximation

Tahir,

Boudraa,

Lamini

et al. 2023

IEEJ Transactions Elec Engng

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Elementary functions are widely integrated in many embedded applications such as speech recognition and signal processing. This paper deals with the issues related to the hardware implementation of those functions. Indeed, a novel efficient Error‐Margin aware Approach for non‐uniform Segmentation of Elementary Functions using degree‐N Polynomial Approximation (EMASEF‐NPA) has been proposed. The bit‐width optimization (BWO) process has been used to obtain a better representation of the approximation polynomial coefficients. The principle of content‐addressable memory (CAM) and Horner's rules have been used in the physical implementation. Functional verification, logical synthesis, and physical implementation were performed using the FPGA platform. The results obtained using EMASEF‐NPA approach show a significant reduction, up to 70%, in the number of segments compared to conventional approaches. The findings of the physical implementation show a considerable decrease in area and delay. © 2023 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC.

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