Efficient generation of pre-silicon MOS model parameters for early circuit design

Abstract

The technology development cycle continues to shrink, which very often requires evaluation of circuit design and technology choices using circuit simulators at the time when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models for advanced CMOS processes. The methodology allows accurate prediction of the full MOS-characteristics for the future technologies combining a constraint back-propagation algorithm based upon a few critical specifications, physical models for the advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on two CMOS production technologies. Good prediction results are achieved: for nMOS the rms error is 1%-2%, for pMOS it is 2%-4%. Index Terms-BSIM3, CMOS modeling, compact modeling. I. INTRODUCTION W ITH THE reduction of the technology development cycle, it becomes increasingly important to be able to predict the performance of the next-generation devices. The ability to do such a prediction would be useful both for early circuit design efforts and technology development. The circuit designers would be provided with SPICE models long before any real silicon is available for model extraction, enabling them to evaluate their circuits under the realistic conditions. Technology groups could use it as a tool to evaluate the device being developed, consider the alternatives, and optimize the device performance for the number of targets and design choices. The attempts at pre-silicon SPICE model generation has previously relied on an extremely time-consuming process and device simulation which is also not very accurate because of lack of good high-field mobility models. Here we propose an efficient methodology that is based on a compact BSIM3v3 device model. Accuracy of results is ensured by the introduction of the constraint back-propagation method. First, accurate physical MOS models are needed. We adopt BSIM3v3 as our main predictive tool, because it is a standard compact model that is well tested and widely used in the industry [1]. It is a physics-based model that accurately models many advanced MOS phenomena. However, we found that some effects that become important with device scaling are not yet included into most commercially available versions of the model, and thus require additional external modeling. These are quantization of inversion-layer charge and velocity overshoot.

Improved effective channel length extraction method for 0.09-0.13 mm CMOS

“…In addition, as MOSFET is being aggressively scaled ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library down, more advanced device characterization and modeling techniques are required [8,9].…”