Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices

Paz, Pedro; Garrido, Mario

doi:10.1007/s11265-023-01867-7

Cited by 11 publications

(2 citation statements)

References 13 publications

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“…Future work will include the evaluation of optimization techniques to further reduce the logic complexity and resource consumption, the development of the other modules of the baseband receiver for these applications and the integration of security modules [8] compliant with the CCSDS 352.0-B-2 and 355.0-B-2 standards. In terms of optimization, for example, the work presented in [31] could be used to implement complex multipliers using three DSPs instead of four.…”

Section: Discussionmentioning

confidence: 99%

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Crocetti,

Pagani,

Bertolucci

et al. 2024

Electronics

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The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards.

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Section: Discussionmentioning

confidence: 99%

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Crocetti,

Pagani,

Bertolucci

et al. 2024

Electronics

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“…As 𝐻 𝑖𝑚 (𝑈 𝑟𝑒 − 𝑈 𝑖𝑚 ) is the common term, ( 8) and ( 9) require only three multipliers [38]. We design them in this research.…”

Section: B Fpga Implementationmentioning

confidence: 99%

Color Diffraction Computer for Incoherent Digital Holography

Hara,

Kakue,

Shimobaba

et al. 2024

IEEE Access

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Incoherent digital holography is a three-dimensional (3D) imaging technique that uses a natural light source. Through computer-based diffraction calculations, 3D information can be reconstructed from self-interferometer-captured holograms. As practical applications require a computer capable of high-speed diffraction calculations, an investigation was conducted into a special-purpose computer that uses a fieldprogrammable gate array (FPGA). This approach had not been used for incoherent digital holography. In this study, the computational performance of a proposed monochromatic diffraction circuit was improved. By using direct memory access transfer, the data transfer time bottleneck, which is a problem in conventional circuits, was eliminated. The calculation was also parallelized, and the processing speed was 150 times faster than that of conventional circuits. In addition, a special-purpose computer for 3D color imaging was developed by implementing the proposed circuits for the three wavelengths on a single FPGA board. As a result of the verification, a speedup of approximately nine times over a 10-core CPU was achieved. The results of this research strongly promote the realization of a holographic portable camera with real-time 3D color imaging capability.INDEX TERMS Field-programmable gate array, image reconstruction, incoherent digital holography, special-purpose computer

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Design and Implementation of an Efficient Vedic Multiplier for Complex Multiplier and Complex MAC Unit in DSP Applications

Ali,

AL-Assfor

2024

2024 5th International Conference on Communications, Information, Electronic and Energy Systems (CIEES)

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Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices

Cited by 11 publications

References 13 publications

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Color Diffraction Computer for Incoherent Digital Holography

Design and Implementation of an Efficient Vedic Multiplier for Complex Multiplier and Complex MAC Unit in DSP Applications

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