Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device

2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

Zang

et al. 2020

This paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). This method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. Therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. The proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon.Index Terms-Carry chains, field-programmable gate array (FPGA), time-of-flight, time-to-digital converter (TDC), Automatic Vehicle.

Section: B Mixed-binning Methodsmentioning

confidence: 99%

Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications

2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

Zang

et al. 2020

“…WCFs make the TDL more even. Due to the clock network, ultra-wide bins commonly appear at the edges of a TDL [48] (R2, Minor 4). To further improve the linearity, we only select a segment of the TDL by changing the start-point and the end-point (see Fig.…”

Section: Software Predictionsmentioning

confidence: 99%

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Wang

IEEE Trans. Ind. Electron.

et al. 2022

This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

“…For FPGA-TDCs, the non-uniformity of carry-chains and clock skews are the two main reasons for nonlinearity [23]. Mismatched dedicated clock distributions in FPGAs cause clock skews, and large clock skews usually appear at the boundaries of clock regions [28]. The non-uniformity of carrychains deteriorates the linearity of entire delay lines and generates ultra-small bins (DNL ≤ -0.90 LSB) and ultra-wide bins.…”

Section: Introductionmentioning

confidence: 99%

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

IEEE Trans. Ind. Electron.

2022

The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, an earlier study concluded that the WU method is not suitable for UltraScale fieldprogrammable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new subtapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDCs combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs.Index Terms-Carry chains, field-programmable gate array (FPGA), time-of-flight (ToF), time-to-digital converter (TDC) Manuscript