Efficient Implementation of VC-1 Decoder on Texas Instrument's OMAP2420 - IVA

Lakshmish, R.; Praveen, K.Y.; Maiti, Kausik; Pai, Joseph Yuh-Shan; Adhikary, Tushar K.

doi:10.1109/iwssip.2007.4381133

Cited by 4 publications

(2 citation statements)

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“…motion-vectors of previous frame for direct MB decoding of B frames, CBP, Intra predictors, left MB pixel columns and top pixel rows (for Loop filtering and overlap transform), need not be stored for all macro-blocks in a frame. Present implementation allocates internal memory to hold these informations only for sufficient number of macroblocks [4].…”

Section: F Memory Optimizationmentioning

confidence: 99%

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

Ramachandra¹,

Satish²

2010

IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS

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High resolution H.264 video contents are present over Internet and local storage devices in huge number thus pushing the need of supporting high definition H.264 video decoding in current generation hand held devices. Texas Instrument's (TI) OMAP3430 (Open Multimedia Applications Platform) is a multimedia processor which is highly used in portable devices. This paper describes the efficient implementation of H.264 Main Profile video decoder on Image and Video Accelerator (IVA) subsystem of OMAP3430 platform. Major focus of current work is on algorithmic, architectural and memory level optimizations. Proposed optimization steps help in achieving real time playback of high resolution H.264 Main Profile contents on hand held devices with high performance and low power consumption.

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Section: F Memory Optimizationmentioning

confidence: 99%

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

Ramachandra¹,

Satish²

2010

IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS

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“…Because VC-1 is a relatively new standard, there are only a few published works. The VC-1 decoders in [16] and [17] are a software solution using OMPA2420 and DM6437, respectively. Just for VC-1 decoding, the performance of the proposed design is 42% better than that of the design in [18].…”

Section: Verification and Implementationmentioning

confidence: 99%

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Cho

Lee

Yoon

et al. 2009

IEICE Trans. Fundamentals

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SUMMARYIn this paper, we present a high-performance VC-1 mainprofile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm 2 . In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications. key words: SMPTE 421M-2006 VC-1, video decoder, transaction level modeling, design space exploration

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A Hardware Task Scheduler for Embedded Video Processing

Alkadi

Terechko

2009

High Performance Embedded Architectures and Compilers

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Efficient Implementation of VC-1 Decoder on Texas Instrument's OMAP2420 - IVA

Cited by 4 publications

References 0 publications

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

A Hardware Task Scheduler for Embedded Video Processing

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