Efficient input support selection for sub-functions in functional decomposition based on information relationship measures

Rawski, Mariusz; Jóźwiak, L.; Łuba, T.

doi:10.1109/eurmic.1999.794453

Cited by 14 publications

(14 citation statements)

References 11 publications

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“…The synthesis results of the proposed KASUMI block cipher implementations for the two architectures 8R and 2R, and the two approaches CL and ROM are shown in Table 1. For the S-BOXes implementation, methods based on the Look-Up- Table (LUT) synthesis 20,21 can be applied. In this paper, the two above mentioned methods are used.…”

Section: Results and Evaluationmentioning

confidence: 99%

An Fpga Implementation of the GPRS Encryption Algorithm 3 (Gea3)

Kitsos

Galanis

Koufopavlou

2005

J CIRCUIT SYST COMP

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The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

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Section: Results and Evaluationmentioning

confidence: 99%

An Fpga Implementation of the GPRS Encryption Algorithm 3 (Gea3)

Kitsos

Galanis

Koufopavlou

2005

J CIRCUIT SYST COMP

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“…Application of blanket algebra to describe the logic dependencies in the FSM presented in Table 1(a). 2,3,5,6,7,9,11,13,14,15,18,19 2,9,12,15,16; 6,7,8,13,17,19,20; 3,4,5; 10,11,14,18}, It is easily verified that blankets presented above satisfy condition (1).…”

Section: Finite State Machinementioning

confidence: 86%

“…The efficiency of functional decomposition has been proved in many theoretical papers. [1][2][3][4] Usually the most important decision to make when designing a state machine is to decide which state encoding to use. A poor choice of codes would result in a state machine that could not be efficiently synthesized with advanced synthesis methods and would result in an implementation that used too much logic resources, or too slow, or both.…”

Section: Introductionmentioning

confidence: 99%

Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition

Rawski

Selvaraj

Łuba

et al. 2006

Int. J. Comp. Intel. Appl.

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This paper presents a Finite State Machine (FSM) implementation method based on symbolic functional decomposition. This novel approach to multilevel logic synthesis of FSMs targets Field Programmable Gate Array (FPGA) architectures. Traditional methods consist of two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However, none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper, the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementation in FPGA architectures. The symbolic functional decomposition does not require a separate encoding step. It accepts FSM description with symbolic states and performs decomposition, producing such a state encoding that guarantees the optimal or near-optimal solution. Keywords: Symbolic functional decomposition; FSM; FPGA. 257 Int. J. Comp. Intel. Appl. 2006.06:257-271. Downloaded from www.worldscientific.com by UNIVERSITY OF AUCKLAND LIBRARY -SERIALS UNIT on 03/15/15. For personal use only.258 M. Rawski et al.

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“…Decomposition allows synthesizing the Boolean function into multilevel structure that is built of components, each of which is in the form of LUT logic block specified by truth tables. Efficiency of functional decomposition has been proved in many theoretical papers [6][7][8][9][10]. However, there are relatively few papers where functional decomposition procedures were compared with analogous synthesis methods used in commercial design tools.…”

Section: Introductionmentioning

confidence: 99%

Digital signal processing designing for FPGA architectures

2007

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This paper presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeted for modern FPGA architectures. Modern programmable structures are equipped with specialized DSP embedded blocks that allow implementing digital signal processing algorithms with use of the methodology known from digital signal processors. On the first place, however, programmable architectures give the designer the possibility to increase efficiency of designed system by exploitation of parallelism of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA) that will boost the performance of designed processing systems. Additionally, application of the functional decomposition based methods, known to be best suited for FPGA structures, allows utilizing possibilities of programmable technology in very high degree. The paper presents results of comparison of different design approaches in this area.

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Efficient input support selection for sub-functions in functional decomposition based on information relationship measures

Cited by 14 publications

References 11 publications

An Fpga Implementation of the GPRS Encryption Algorithm 3 (Gea3)

An Fpga Implementation of the GPRS Encryption Algorithm 3 (Gea3)

Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition

Digital signal processing designing for FPGA architectures

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