Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

Kim, Dooyoung; Kim, Jinuk; Ibtesam, Muhammad; Solangi, Umair Saeed; Park, Sung-Ju

doi:10.5573/jsts.2020.20.4.390

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…For each clock cycle, data enters the scan-chain at data_in and ends at scan chain data_out, the behavior of this scan chain is controlled by the scan_en signal as shown in the following figures. In the scan chain process, there are potential failures caused among others by stuck-atfaults and timing faults among others is excessive test power consumption, to overcome this some authors propose scan-chain architecture to reduce test power consumption such as [15]. An indication of the failure of the scan chain is a very low or zero yield, even today where modern chips are based on nanometer technology, some researchers propose a low cost method for stuck-at-fault problems where the method of diagnosing the problem is claimed to be effective, low complexity, solution suitable as Dounavi et al proposed [16], the above hardware-assisted diagnostic method is claimed to be better than the simulation diagnostic method, but due to the considerable overhead, the method is said to be not accepted in practical designs, therefore Ahlawat et al proposed the hardware-assisted method following the previous method and the proposed design has less gate overhead in terms of area and performance [17].…”

Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.

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Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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“…The method in [ 29 ] merged the scan cells with higher care bit density toward the front of scan chains. Kim et al proposed a new shift mechanism of exclusive scan-shift and the scan chain reordering method considering the number of the scan cell’s fan-outs [ 30 ]. Lee et al proposed the scan chain stitching method using the circuit topology to analyze the testability of each flip-flop [ 31 ].…”

Section: Related Workmentioning

confidence: 99%

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Lee

Cho

Kim

et al. 2021

Sensors

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Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

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Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

Cited by 2 publications

References 7 publications

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

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