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The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

The modern automobile industry is rapidly shifting toward the era of self-driving cars. Due to rapid technological development, many mechanical parts in automobiles have been switched to electronic devices. Therefore, the proportion of electronic devices in modern cars is increasing. Even though many parts have been replaced by electronic devices, vehicles still require the periodic maintenance not only for mechanical parts, but also for automotive electronics. To guarantee the high reliability of automotive Application-Specific Integrated Circuits (ASICs), automotive chips are tested during manufacturing for functional and structural defects. Moreover, automobile chips are also tested using several in-field diagnostic techniques (e.g., online Built-In Self-Test (BIST), Software-Based Self-Test (SBST)) while the chips are operating. By using these in-field diagnostic techniques, functional and structural defects in automotive ASICs, which occur in the early-life cycle and normal operation, can be detected. However, automotive semiconductor devices still require testing for aging-induced defects and soft errors to prevent critical functional failures. Moreover, aging-induced defects are hard to detect with conventional in-field diagnostic techniques which is based on BIST techniques. Thus, this work presents a secure Controller Area Network (CAN)-based Test Access Mechanism (TAM) for aging defect diagnosis with efficient soft-error resilient scan cell design for automotive ASICs. The proposed TAM incurs area overhead of 6% to 9% depending upon the selection of mode identification. Further, the proposed Aging monitoring and Soft Error Resilience Flip Flop (ARFF) incurs 22% less area and power as compared to separate implementation of the Built-In Soft Error Resilience (BISER) and the Early Capture Flip Flop (ECFF).

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