The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

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The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.