Efficient Macro-code Emulation In Hardwired Pipelined Processors

Mulder, J. M.; Portier, R. J.; Srivastava, A.; Velt, R. in't

doi:10.1109/micro.1988.639261

Cited by 2 publications

(3 citation statements)

References 3 publications

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“…The emulation facility of the architecture framework is dedicated towards this goal [3]. Scalability of implementation complexity is an important feature when implementatioa constraints disallow integration of the whole architectural functionality.…”

Section: 1mentioning

confidence: 99%

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An architecture framework for application-specific and scalable architectures

Mulder

Portier

Srivastava

et al. 1989

Proceedings of the 16th Annual International Symposium on Computer Architecture - ISCA '89

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Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The Scalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific aschitectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be reta.rgeted quickly to fit the applicationspecific architecture;This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.

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Section: 1mentioning

confidence: 99%

“…First, for emulation and interrupt efficiency, emulations should be continuously interruptible without the overhead of saving the state in registers or memory [3]. Second, control-transfer to the appropriate emulation routine should be immediate.…”

Section: 7mentioning

confidence: 99%

An architecture framework for application-specific and scalable architectures

Mulder

Portier

Srivastava

et al. 1989

Proceedings of the 16th Annual International Symposium on Computer Architecture - ISCA '89

Self Cite

View full text Add to dashboard Cite

show abstract

“…The emulation fa.ci.lity of the architecture framework is dedicated towards this goal [3]. Scalability of implementation complexity is an important feature when implementation constraints disallow integration of the whole architectural functionality.…”

Section: Three-way Scalabilitymentioning

confidence: 99%

An Architecture Framework For Application-specific And Scalable Architectures

Mulder¹,

Portier²,

Srivastava³

et al.

The 16th Annual International Symposium on Computer Architecture

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Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the applicationspecific architecture;This paper concentrafw primarily on the architecture framework of SCARCE, but RIW presents briefly some software issues and outlines the process of generating VLSI processors.

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Efficient Macro-code Emulation In Hardwired Pipelined Processors

Cited by 2 publications

References 3 publications

An architecture framework for application-specific and scalable architectures

An architecture framework for application-specific and scalable architectures

An Architecture Framework For Application-specific And Scalable Architectures

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