Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates

Thangkhiew, Phrangboklang Lyngton; Gharpinde, Rahul; Datta, Kamalika

doi:10.1109/tcsi.2018.2792474

Cited by 50 publications

(29 citation statements)

References 29 publications

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“…MAGIC and IMPLY logic families are widely explored in the literature. Authors of [12] [28][29][30][31] have presented several approaches where logic functions are broken down into several MAGIC or IMPLY operations. These operations are then performed sequentially inside memristive crossbar arrays.…”

Section: B Limitationsmentioning

confidence: 99%

“…As explained in Section V-B, the proposed memristive computational memory is able to perform any general arithmetic function by breaking it into a netlist of iterative MOL operations. As MOL is based on the primitive AND/OR operations, the ABC tool [45], which has been employed for existing logic design styles [30] [31], could be also leveraged in order to realize the synthesis task. This will be considered in our future work.…”

Section: Comparisonmentioning

confidence: 99%

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Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Ali

Rizk

Baghdadi

et al. 2020

IEEE Trans. VLSI Syst.

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In this paper, we present a novel logic design style, namely memristor overwrite logic (MOL), associated with an original MOL-based computational memory. MOL relies on a fully digital representation of memristor and can operate with different memristive device technologies. Its integration in memristive crossbar arrays and computational memories allows the execution of bit and vector-level primitive logic operations in two computational steps at most. Promising features and performances are demonstrated through the implementation of N-bit full addition using the proposed MOL-based computational memory.

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Section: B Limitationsmentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%

Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Ali

Rizk

Baghdadi

et al. 2020

IEEE Trans. VLSI Syst.

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“…The MAGIC gates are realized by the RRAM devices connected in series and/or in parallel [5]. The design practices of logic circuits with the MAGIC gates were reported [14][15], and the synthesis methods were studied [16][17]. Nevertheless, the circuit performance decreases for some logic functions, because only the NOR and NOT MAGIC gates can be implemented in the RRAM array.…”

Section: Introductionmentioning

confidence: 99%

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates

Cui

Wei

et al. 2021

IEEE Access

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The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family. The advantages of the proposed NMOS-like RRAM gates include: (1) all the gate circuits are array-implementable; (2) the gate family is logic complete; (3) the NOR, AND and NOT gates only consume single cycle respectively in the computation phase; (4) the gate circuits save half number of RRAM devices compared with the CMOS-like RRAM based counterparts. Furthermore, the synthesis method of logic circuits based on the NMOS-like RRAM gates is proposed and discussed. The single-cycle NMOS-like RRAM gates are utilized in priority under the constraints of the logic block. The features of the proposed synthesis method are: (1) it generates the high-performance logic circuits because the NMOS-like RRAM based gates work in parallel; (2) the logic block based on the proposed NMOS-like gates can be realized in the RRAM array; (3) the large-scale logic functions can be implemented by cascading the logic blocks. The in-array full-adder circuit generated by the proposed synthesis method only consumes three cycles in minimum, which outperforms the previous RRAM based counterpart. The synthesis results on the benchmark circuits show that the proposed synthesis method is able to generate the high-performance circuit in RRAM arrays for arbitrary logic functions. INDEX TERMS RRAM Array, NMOS-like RRAM Gates, Computation in Memory, Synthesis Method.

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“…The mapping‐process inside the sliced crossbar‐arrays [13] differs from the contemporary mapping‐techniques in [8, 10–12] where the nodes in any particular level of the AIG ([8, 12]) or BDD ([10, 11]) (for any input Boolean function) are simultaneously mapped in the different rows of the crossbar‐array (a set of such component crossbar‐arrays comprise the memristive‐memory [31]). However, the number of nodes mapped per crossbar‐array may vary depending upon the component crossbar‐array size, and the availability of the free‐rows inside each of such crossbar‐arrays.…”

Section: Introductionmentioning

confidence: 99%

“…As the primary goal of this work is to map the input Boolean functions efficiently inside a cluster of crossbar‐slices, thus the complexity of the MPU‐controller has not been analysed in the present work. However, any of the existing controller‐designs reported in [17, 18, 32] can be used to serve the purpose.…”

Section: Introductionmentioning

confidence: 99%

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Chakraborty

Maurya

Prasad

et al. 2020

IET Computers & Digital Tech

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Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture.

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Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates

Cited by 50 publications

References 29 publications

Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

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