Efficient memory ip design for HDTV coding applications

Hsia, Shih-Chang

doi:10.1109/tcsvt.2003.813418

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Vlsi Architecture and Chip Implementation1

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Cited by 12 publications

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“…Thus we employ the temporal registers R0~R15 to store the pixels for data re-ordering. The memory access and addressing design can refer to our previous paper [17].…”

Section: Vlsi Architecture and Chip Implementationmentioning

confidence: 99%

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

Hsia

Tsai

Wang

et al. 2009

J Sign Process Syst Sign Image Video Technol

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This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8×8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm 2 using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3~1/5 of the conventional DCT chips.

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“…Thus we employ the temporal registers R0~R15 to store the pixels for data re-ordering. The memory access and addressing design can refer to our previous paper [17].…”

Section: Vlsi Architecture and Chip Implementationmentioning

confidence: 99%