Efficient Mitigation of SET Induced Harmonic Errors in Ring Oscillators

Agustin, Javier; López‐Vallejo, Marisa; Soriano, Carlos Gil; Cholbi, Pablo; Massengill, L.W.; Chen, Yanran P.

doi:10.1109/tns.2015.2496169

Cited by 9 publications

(6 citation statements)

References 13 publications

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“…Besides long term TID effects, energetic particles generate transients or upsets on nodes that do not contain TMR (if a particle only affects a single node) or nodes that are not heavily decoupled. Various designs have been discussed to obtain a Radiation Hardened By Design PLL based on ring oscillator topologies [8]- [11] and LC structures [12]- [14], also for various technologies [15]. Especially the loop filter has been known to be a sensitive node [16]- [18].…”

Section: Introductionmentioning

confidence: 99%

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity

Prinzie

Christiansen

Moreira

et al. 2017

IEEE Trans. Nucl. Sci.

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Abstract-In this work, a comparison has been made between a low noise ring-oscillator and an LC-oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation experiments targeting high-energy physics applications. Two different samples were irradiated up to a total ionizing dose (TID) in SiO2 of 200 Mrad and 600 Mrad with a 100• C thermal annealing step. Single-Event Upset (SEU) tests were performed with heavy ions with LETs (Linear Energy Transfer) between 3.2 and 69.2 MeV.cm 2 /mg. A Two-photon absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. Both independent PLLs have identical loop dynamics to allow a fair comparison including a Triple-Modular Redundant (TMR) divider and TMR phase detector. Furthermore these circuits consume the same amount of power. The PLLs were processed in a commercial 65 nm CMOS technology.

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Section: Introductionmentioning

confidence: 99%

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity

Prinzie

Christiansen

Moreira

et al. 2017

IEEE Trans. Nucl. Sci.

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“…That problem is called harmonic induced error because a single event transient (SET) produced by the impact of a particle can shift the frequency of a ring oscillator from its fundamental frequency to the third harmonic of that frequency. Using an asymmetric ring oscillator with internal duty cycles different from 50% solves the problem because SETs are completely masked [20].…”

Section: Discussionmentioning

confidence: 99%

“…Replacing (34) and (35) in (19) and (20), and at each node with individually controlled bias voltages are:…”

Section: B Soft Duty Cycle Configurationmentioning

confidence: 99%

An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle

Agustin

López‐Vallejo

2015

IEEE Trans. Circuits Syst. I

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Ring oscillators are used in many applications, but for all of them the system output is a clock signal with a 50% duty cycle. Our work sets the analytical basis for understanding and designing a ring oscillator whose outputs are clock signals with fully-configurable duty cycles different from 50%. We present two models in order to vary the output duty cycle with reduced area overhead: the first model is based on the layout design, focusing on the transistor sizing of each inverter gate; and the second model establishes a relation between the output duty cycle and different bias voltage schemes. These models are validated by simulation with a 40 nm commercial technology. The simulations include the impact of variability and the characterization of the oscillator phase noise. We also discuss the utilization of our new approach in many different applications for heterogeneous environments.

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“…A voltage switching charge pump was used to reduce the SET sensitivity in a single ended ring VCO-based PLL [8]. Mitigating harmonic errors induced by the SET in a single ended inverter ring-based oscillator was proposed in [9]. Similarly, the SET effect on differential ring VCOs were studied in [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

“…This phase displacement causes interference in transceivers and data loss in communication links. Several studies have focussed on the hardening of the VCOs for radiation environments [5][6][7][8][9][10][11][12]. The Triple modular redundancy (TMR) technique is a widely adopted approach to prevent SEEs in PLL circuits [5,6].…”

Section: Introductionmentioning

confidence: 99%

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

Karthigeyan¹,

Radha²,

Manikandan

2021

IET Circuits, Devices & Syst

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Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in the sub-100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage-controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor-voltage controlled oscillator (LC-VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC-VCOs that have an inherent rad-hard capability which proves a significant improvement in SET sensitivity. K E Y W O R D S radiation hardening (electronics), voltage-controlled oscillatorsThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Efficient Mitigation of SET Induced Harmonic Errors in Ring Oscillators

Cited by 9 publications

References 13 publications

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity

An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

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