Efficient Modeling Techniques for Dynamic Voltage Drop Analysis

Harizi,; Haussler,; Olbrich,; Barke,

doi:10.1109/dac.2007.375255

Cited by 3 publications

(5 citation statements)

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“…Consequently, we noted that fluctuations in power supply voltage while switching [19] result in an imprecise prediction of RMS current.…”

Section: Incorporating Ir Drop Effectsmentioning

confidence: 96%

“…From (19) and (20), it is apparent that change in power supply voltage has a linear dependence on change in slew of the driving point voltage waveform. Accurate results in the prediction of RMS current have been obtained by modeling the output slew.…”

Section: Incorporating Ir Drop Effectsmentioning

confidence: 97%

“…RMS currents and the peak drive current relate to the operating headroom in a nonlinear fashion as (19) Also by assuming the driver output current to be a triangular waveform, it can be stated that [11] (20)…”

Section: Incorporating Ir Drop Effectsmentioning

confidence: 99%

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Accurate Current Estimation for Interconnect Reliability Analysis

Jain

2012

IEEE Trans. VLSI Syst.

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An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the net's lumped capacitance or the net's effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective "EM" slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the first time, we present a method for incorporating the driver's dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure.

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“…Consequently, we noted that fluctuations in power supply voltage while switching [19] result in an imprecise prediction of RMS current.…”

Section: Incorporating Ir Drop Effectsmentioning

confidence: 96%

Section: Incorporating Ir Drop Effectsmentioning

confidence: 97%

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Accurate Current Estimation for Interconnect Reliability Analysis

Jain

2012

IEEE Trans. VLSI Syst.

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“…Using the corresponding CSM model for each instance in the netlist, the new model provides a voltage drop analysis error less of +10 % in VDP value and about +4 % in VDP time at block level [5]. The overestimation is due to the fact, that the input/output transition times used in CSM are estimated using a standard STA approach (based on PrimeTime), which implicitly assumes that within the circuit the power supply voltage is uniformly constant at each cell.…”

Section: Cells With Multiple Input Switching Transitionsmentioning

confidence: 99%

Fast analysis of on-chip power distribution networks

Harizi

2011

2011 IEEE Symposium on Computers &Amp; Informatics

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The verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has also grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyze power distribution networks in the time-domain. The new contributions of this work are the use of PWL data point reduction and correction factors (CF) to reduce the number of current source models and to speed up the characterization time. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 400, although the cell pre-characterization is based on SPICE simulations. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The runtime and accuracy of the proposed approach are demonstrated on some industrial designs.

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“…Furthermore, clock-gating, power-gating and other power saving techniques have undesired side-effects of increasing variability of current drawn by different cores which causes additional supply voltage fluctuations. The semiconductor industry has already moved to dynamic voltage drop (DVD) analysis [8] in order to account for the contribution of power density, variations in switching activity profile and impact of inductance and decaps. DVD also captures the impact of spatial and temporal switching events.…”

Section: Runtime Supply Voltage and Temperature Variationsmentioning

confidence: 99%

Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links

Nigussie

Plosila

Isoaho

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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we present a runtime power supply and temperature variation tolerance technique for delay-insensitive on-chip communication links. Signal integrity of a current sensing receiver is affected by runtime supply voltage and temperature fluctuations. By monitoring receiver's input current and comparing it with receiver's reference current, the effect of variation on link reliability is detected. Receiver reconfiguration and request for retransmission is carried out when error is detected. This scheme makes the link adaptive to the effect of variations enabling continuous and reliable operation of the link. The power consumption due to monitoring is 489µW for a 2mm link, which is 1.63% of a 64-bit 1-of-4 encoded link's power consumption. It requires only 5.83µm 2 additional active area. The circuits are designed and simulated in Cadence Analog Spectre using 65nm CMOS technology from STMicroelectronics.

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Efficient Modeling Techniques for Dynamic Voltage Drop Analysis

Cited by 3 publications

References 0 publications

Accurate Current Estimation for Interconnect Reliability Analysis

Accurate Current Estimation for Interconnect Reliability Analysis

Fast analysis of on-chip power distribution networks

Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links

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