Efficient Monte Carlo-based analog parametric fault modelling

Stratigopoulos, Haralampos-G.; Sunter, Stephen

doi:10.1109/vts.2014.6818741

Cited by 14 publications

(6 citation statements)

References 19 publications

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“…Monte Carlo [10] is one of the most widely used methods to model parametric variations based on random combinations of values that are selected within the range of each parameter. However, the repetitive random sampling process is required for each defect to acquire more accurate results on the behavior of a circuit.…”

Section: E Monte Carlo Simulationmentioning

confidence: 99%

“…These sampling techniques are easier to implement with respect to the others. In [10], [47], authors made a reasonable effort to reduce the simulation time of the Monte Carlo technique. Monte Carlo methods usually generate a large number of samples of predictable manufacturing deviations in a circuit and then only simulate those samples that are most likely to generate failing or marginally passing circuits.…”

Section: E Monte Carlo Simulationmentioning

confidence: 99%

“…In literature, researchers from industry and academia suggested different techniques to reduce the overall simulation time required to simulate an entire set of defects, named defect universe [4]. These techniques include parallel simulation on different cores [7], analysis in the frequency domain at specific operating points [8], usage of high-level models [9], Monte Carlo-based simulations [10], or fault sensitivity analysis [11]. Other techniques aim at reducing the set of defects that need to be simulated, e.g., with fault grouping techniques.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Azam

Dall'Ora

Fraccaroli

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field.Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.

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Section: E Monte Carlo Simulationmentioning

confidence: 99%

Section: E Monte Carlo Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Azam

Dall'Ora

Fraccaroli

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…However, such techniques have not been materialized yet due to the difficulty in defining the fault model [4,26]. Another technique is built-off test, which involves migrating some of the instrumentation in the ATE onto the test board [10,14].…”

Section: Introductionmentioning

confidence: 99%

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors

et al. 2015

Self Cite

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International audienceTesting the RF functions of systems-on-chip incurs a very high cost. Built-in test is a promising alternative to facilitate testing and reduce cost. However, designing built-in test circuits that tap into the sensitive RF signal paths, in order to extract useful information for the purpose of testing, often finds the designers reluctant since it results in some performance degradation that needs to be accounted for during the design. In this paper, we study a transparent built-in test approach based on non-intrusive sensors that are not electrically connected to the RF circuit under test. The non-intrusive sensors simply monitor process variations and by virtue of this they are capable of tracking variations in the performances of the RF circuit as well. The alternate test paradigm is employed to map the outputs of the sensors to the performances, in order to replace the standard tests for measuring the performances directly. We discuss in this paper the principle of operation of these sensors and we demonstrate the non-intrusive test approach on a 65nm RF low noise amplifier

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“…Other fault models, such as open line, inline resistance fault (IRF) [12] and analog parameter fault [13], etc. are also useful to model the realistic faults in circuits.…”

Section: Introductionmentioning

confidence: 99%

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Tang

et al. 2014

2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing

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An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault category's subcategories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.

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Efficient Monte Carlo-based analog parametric fault modelling

Cited by 14 publications

References 19 publications

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

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