Efficient online and offline testing of embedded DRAMs

Abstract

AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

“…As mentioned, Self-adjusting Output Data Compression [11], [12], [13] is based on the exploitation of the fact that Dynamic RAMs refresh data during Read/Write operations and during periodic refresh operations, in order to avoid data retention. In typical word-organized DRAMs ( Figure 1), a Read/Write operation first transfers the contents of the memory word indicated by the Address signal to the Refreshment Register where the operation is performed before the result is written back to memory.…”

“…The work of Olivo and Dalpasso triggered the idea of Self adjusting Output Data Compression (SODC), in [11], [12], [13]. The basic idea underlying SODC is the calculation of a characteristic of the memory contents, denoted by C ref ; the characteristic is periodically calculated, stored in another location (C test ) and compared to the stored value of C ref to reveal inconsistencies.…”

“…Furthermore, it has been shown, with simulations based on data from both random experiments and real programs, that self-adjusting output data compression provides for lower detection latency and higher average detection probability than on-line checking schemes relying on parity codes [12], [13].…”

Multiple Errors Detection Technique for RAM

“…After checking procedure Controller releases the RAM interface and generates the output signal "busy=0". As it was shown in [7] such built-in architecture may be successfully implemented for DRAM without time penalty for read access.…”

“…Both on-line and off-line testing could be done using SelfAdjusting Output Data Compression [6][7][8]. To perform testing two RAM characteristics obtained as modulo-2 sum of all addresses, where memory cell stores non-zero value.…”