Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs

Kruppe, Hanna; Sommer, Lukas; Weber, Lukas; Oppermann, Julian; Axenie, Cristian; Koch, Andreas

doi:10.1007/978-3-031-04580-6_16

Cited by 2 publications

(2 citation statements)

References 21 publications

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“…This work produced an implementation of a Bragg peak detection DNN which achieved a throughput improvement of 4× over the previous state of the art. This work also produced ILP and CP-SAT models for Shared Operator Scheduling (Kruppe et al, 2021) and a novel lifting approach for enabling domain scientists to perform transformations on low-level representations of DNNs.…”

Section: Discussionmentioning

confidence: 99%

“…-Key technical contribution of this work: A CP-SAT formulation of the Shared Operator Scheduling (Kruppe et al, 2021); a lifting method for raising MLIR to Python to enable domain-specific and user-extensible transformations on low-level representations of DNNs; finally, an implementation of the BraggNN (Liu et al, 2022b) network (for Bragg peak detection) which achieved a throughput 4.8µ s/sample, i.e., a 4× improvement over the previous state of the art.…”

Section: Contributionsmentioning

confidence: 99%

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Section: Discussionmentioning

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An End-to-End Programming Model for AI Engine Architectures

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FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis

Choi

Santillana

Shen

et al. 2023

ACM Trans. Reconfigurable Technol. Syst.

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Probabilistic Sentential Decision Diagrams (PSDDs) provide efficient methods for modeling and reasoning with probability distributions in the presence of massive logical constraints. PSDDs can also be synthesized from graphical models such as Bayesian networks (BNs) therefore offering a new set of tools for performing inference on these models (in time linear in the PSDD size). Despite these favorable characteristics of PSDDs, we have found multiple challenges in PSDD’s FPGA acceleration. Problems include limited parallelism, data dependency, and small pipeline iterations. In this paper, we propose several optimization techniques to solve these issues with novel pipeline scheduling and parallelization schemes. We designed the PSDD kernel with a high-level synthesis (HLS) tool for ease of implementation and verified it on Xilinx Alveo U250 board. Experimental results show that our methods improve the baseline FPGA HLS implementation performance by 2,200X and the multicore CPU implementation by 20X. The proposed design also outperforms state-of-the-art BN and Sum Product Network (SPN) accelerators that store the graph information in memory.

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Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs

Cited by 2 publications

References 21 publications

An End-to-End Programming Model for AI Engine Architectures

An End-to-End Programming Model for AI Engine Architectures

FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis

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