Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor

Abstract

Memristive logic‐in‐memory (LIM) is an attractive candidate for in‐memory computing and thus would overcome some of the issues concerning the von Neumann bottleneck, which has been intensively investigated. Here, a multi‐bit and functionally complete LIM strategy is designed to efficiently perform multi logical functions in parallel. This strategy is experimentally demonstrated by a multi‐bit ferroelectric tunnel junction (FTJ) memristor with a sub‐nanosecond operation speed which is nearly two orders of magnitude faster than the previous memristive LIM. Using the four resistance states (2‐bit) of only a single FTJ memristor cell, two logical computations are successfully performed in parallel, and the 16 complete Boolean logic functions are implemented within only two steps. In addition, the multi‐encoding schemes are proposed to further improve the efficiency and flexibility of parallel logical computations. Accordingly, the 1‐bit binary full adder can be implemented using as less as three parallel memristors by only performing five steps, and on this basis the N‐bit full adder can also be realized. These results provide a highly efficient LIM approach, which could be a promising candidate for future computing architecture.

Highly Reliable Logic-in-Memory by Bidirectional Built-in Electric-Field-Modulated Multistate IGZO/AFE Nonvolatile Memory

“…Multistate NVMs in principle have the potential to design a parallel LIM with multilogic operations. − Figure a shows the schematic diagram of a widely studied LIM architecture based on a binary two-terminal NVM. The input signals to the TE and BE of the NVM are denoted as T 1 and T 2 , and the initial and final states of the NVM are denoted by Z 1 and Z 1 ′, respectively.…”

Efficient Method for Error Detection and Correction in In‐Memory Computing Based on Reliable Ex‐Logic Gates

“…Despite the advantages of the proposed EDCM, the generation of ME and IC bits may require additional peripheral circuits for converting output bits when two input bits are the result of the cascaded logic gates. Designing the efficient peripheral circuit for the proposed EDCM would be further work but feasible using the multiplexers [32] or transimpedance amplifiers, [33,34] which are often used in the in-memory computing of vector-matrix multiplication. For instance, the two-input NOR operation for the two outputs of the cascaded logic gates can be achieved using transimpedance amplifiers with the same detection and correction sequence but a longer time, as shown in Figure S5 in Section S9 of online Supporting Information.…”

Van der Waals Ferroelectric Semiconductor Field Effect Transistor for In-Memory Computing

“…There have been several types of in-memory computing models, such as charge-based, − resistive switching, , and tunneling-based in-memory computing . Among those models, charge-based in-memory computing cells, which utilize a floating gate, − interface charge trapping, − and ferroelectric polarization switching , to storage charges in combination with a semiconductor-based transistor to execute logic operations, are compatible with current complementary metal-oxide semiconductor (CMOS) processes and have received wide attention.…”

“…Ferroelectricity, a phenomenon of spontaneous electrical polarization, holds great potential for in-memory computing because of the nonvolatility of the polarization, nondestructive readout, and fast signal switching. − Ferroelectric insulators such as poly­(vinylidene fluoridetrifluoroethylene) (P­(VDF-TrFE)), Hf 0.5 Zr 0.5 O 2 , , and BiTiO 3 , as the memorial dielectric layer or tunneling layer, have been demonstrated for in-memory computing. However, as the device size is scaled down, the spontaneous polarization of bulk ferroelectric materials fades away with incomplete screening of the polarization-bound charges, undesired surface reconstruction, and reduced long-range Coulomb coupling. − …”