Efficient pipeline FFT processors for WLAN MIMO-OFDM systems

Sansaloni, T.; Perez-Pascual, A.; Torres, V.; Valls, Javier

doi:10.1049/el:20052597

Cited by 40 publications

(29 citation statements)

References 3 publications

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“…On the other hand, MDC pipeline method which is consisted of multi-I/O paths and parallel architecture has the increased throughput in proportion to the number of multi-I/O paths in MIMO-OFDM systems. Therefore, MDC pipeline method is suitable method for MIMO-OFDM systems and the architectures based on MDC pipeline method are recently proposed such as R2MDC, R4MDC, R8MDC and mixed-radix MDC (MRMDC) [2,3].…”

Section: Conventional Fft Processor For Mimo-ofdm Systemsmentioning

confidence: 99%

“…2 (a) shows the required area comparison of the proposed method and the conventional methods at 1 × 1 channel to 8 × 8 channels. The area of a complex multiplier converts to 50 adders for the equivalent comparison of conventional methods if a 16-bit precision and the scheme of three real multiplier and five real adders is considered in its implementation [3]. To obtain the variable comparison, we add the R2MDC to the methods of Table I.…”

Section: Proposed Multi-input R2 Sdf-kr For Mimo-ofdm Systemsmentioning

confidence: 99%

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Multi-input R23SDF-kR for efficient FFT processor in MIMO-OFDM systems

Lee

Kim

Wang

et al. 2009

IEICE Electron. Express

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Abstract:In this paper, we propose a multi-input R2 3 SDF-kR architecture for efficient FFT processor in MIMO-OFDM systems with n-antennas at the transmitter and receiver. The proposed architecture is based on R2 3 SDF for low complexity and it is operated to k times clock rate for multi-stream processing like MDC pipeline method in MIMO-OFDM systems. The proposed multi-input R2 3 SDF-kR processor reduces the hardware complexity with similar or less computation in comparison of conventional MDC methods. Comparison results show that the proposed R2 3 SDF-4R and R2 3 SDF-8R reduce the area about 58% and 76% compared with the most area-efficient methods at 4 × 4 and 8 × 8 MIMO channels, respectively.

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Section: Conventional Fft Processor For Mimo-ofdm Systemsmentioning

confidence: 99%

Section: Proposed Multi-input R2 Sdf-kr For Mimo-ofdm Systemsmentioning

confidence: 99%

Multi-input R23SDF-kR for efficient FFT processor in MIMO-OFDM systems

Lee

Kim

Wang

et al. 2009

IEICE Electron. Express

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“…Several different architectures have been proposed, based on different decomposition methods, such as the Radix-2 Multipath Delay Commutator (R2MDC) [1], Radix-2 Single-Path Delay Feedback (R2SDF) [2], Radix-4 Single-Path Delay Commutator (R4SDC) [3], and Radix-2 2 Single-Path Delay Feedback (R2 2 SDF) [4]. More recently, Radix-2 2 to Radix-2 4 SDF FFTs were studied and compared in [5]; in [6] an R2 3 SDF was implemented and shown to be area efficient for 2 or 3 multipath channels. Each of these architectures can be classified as multipath or single-path.…”

Section: Introductionmentioning

confidence: 99%

Pipeline FFT Architectures Optimized for FPGAs

Zhou

Peng

Hwang

2009

International Journal of Reconfigurable Computing

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This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R2 2 SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice. The R4SDC architecture ran at 123.8 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice. On Virtex-4, the 16-bit 1024-point R2 2 SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2 MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio. The R2 2 SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.

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“…Monoprocessor architectures such as [5] have to be discarded, as they are not able to fulfill the timing specifications. The throughput can be increased by using either parallel [6,7] or pipeline architectures [8][9][10][11][12][13][14]. Pipeline architectures present smaller latency and lower-power consumption [8,9], which makes them suitable for mobile devices such as DVB-T/DVB-H receivers.…”

Section: Introductionmentioning

confidence: 99%

An FFT Core for DVB‐T/DVB‐H Receivers

et al. 2008

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This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB-T/DVB-H receivers. The proposed core is based on a pipeline radix-2 2 SDF architecture. The necessary changes in the radix-2 2 SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB-T/DVB-H. Area and power results are provided for the proposed core.

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Efficient pipeline FFT processors for WLAN MIMO-OFDM systems

Cited by 40 publications

References 3 publications

Multi-input R23SDF-kR for efficient FFT processor in MIMO-OFDM systems

Multi-input R23SDF-kR for efficient FFT processor in MIMO-OFDM systems

Pipeline FFT Architectures Optimized for FPGAs

An FFT Core for DVB‐T/DVB‐H Receivers

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