An FFT Core for DVB‐T/DVB‐H Receivers

Cortés, A.; Vélez, Igone; Zalbide, Ibon; Irizar, A.; Sevillano, Juan F.

doi:10.1155/2008/610420

Cited by 17 publications

(21 citation statements)

References 13 publications

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“…Complexity results refer to gate and memory complexity in silicon for a 90 nm CMOS technology and standardcells library. The comparison includes an application-specific instruction set processor (ASIP) [23], two macrocells specifically designed for DVB-T (see [24,42]) and a macrocell obtained by an automatic IP generator [10]. Note that the proposed cascade macrocell stands for its low complexity while maintaining similar application [37], whose target is the real-time implementation of a 128-point 528-MSamples/s FFT.…”

Section: Implementation Results and Comparison With The State-of-the-artmentioning

confidence: 99%

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Saponara

Rovini

Fanucci

et al. 2011

Circuits Syst Signal Process

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The design of Fast Fourier Transform (FFT) integrated architectures for System-on-Chip (SoC) telecom applications is addressed in this paper. After reviewing the FFT processing requirements of wireless and wired Orthogonal Frequency Division Multiplexing (OFDM) standards, including the emerging Multiple Input Multiple Output (MIMO) and OFDM Access (OFDMA) schemes, three FFT architectures are proposed: a fully parallel, a pipelined cascade and an in-place variable-size architecture, which offer different trade-offs among flexibility, processing speed and complexity. Silicon implementation results and comparisons with the state-of-the-art prove that each macrocell outperforms the known works for a target application. The fully parallel is optimized for throughput requirements up to several GSamples/s enabling Ultra-wideband (UWB) communications by using all channels foreseen in the standard. The pipelined cascade macrocell minimizes complexity for large size FFTs sustaining throughput up to 100 MSamples/s. The in-place variable-size FFT macrocell stands for its flexibility by allowing run-time reconfigurability required in OFDMA schemes while attaining the required throughput to support MIMO communications. The three architectures are also compared with common case-studies and target technology

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Section: Implementation Results and Comparison With The State-of-the-artmentioning

confidence: 99%

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Saponara

Rovini

Fanucci

et al. 2011

Circuits Syst Signal Process

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show abstract

“…throughput and numerical accuracy) identical or similar to those of this work. The comparison includes an application specific instruction set processor (ASIP) [12], a macrocell specifically designed for DVB-T [3] and a macrocell obtained by an automatic generation tool [5]. Note that the macrocell generated by the tool proposed in this work shows the lowest complexity while maintaining similar application performance (throughput of 9 Msample/s, SQNR greater than 40 dB, programmable transform length between 2048 and 8192).…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…As explained in section 3.1, SWL in fixedpoint arithmetic should be increased in each stage to avoid overflow in the data-path (in this case SWL should vary from 10 bits to 19 bits to preserve the 8 bit accuracy at the output). However most IP cores in literature [5,13] sets IOWL=SWL=constant and pick up an intermediate value between the two extremes. It is clear from Figure 7 how both BFP and CBFP approaches outperform fixed-point arithmetic even with small values of SWL.…”

Section: Fft/ifft Core Configurationmentioning

confidence: 99%

See 1 more Smart Citation

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems

L'Insalata¹,

Saponara²,

Fanucci³

et al. 2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy

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“…The design presented in [13] implements a 2K/4K/8K multimode FFT and achieves 9 MHz clock frequency, at a computation time of up to 450 μs. Finally, a single ASIC chip, systolic FFT processor, developed by the Mayo Foundation computes 4096-point FFTs sustaining a throughput of 200 Ms/s [26].…”

Section: Architecture's Performance and Advantagesmentioning

confidence: 99%

Fully Systolic FFT Architecture for Giga-sample Applications

Babionitakis

Chouliaras

Manolopoulos

et al. 2009

J Sign Process Syst Sign Image Video Technol

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We present a novel 4096 complex-point, fully systolic VLSI FFT architecture based on the combination of three consecutive radix-4 stages resulting in a 64-point FFT engine. The outcome of cascading these 64-point FFT engines is an improved architecture that efficiently processes large input data sets in real time. Using 64-point FFT engines reduces the buffering and the latency to one third of a fully unfolded radix-4 architecture, while the radix-4 schema simplifies the calculations within each engine. The proposed 4096 complex point architecture has been implemented on a FPGA achieving a post-route clock frequency of 200 MHz resulting in a sustained throughput of 4096 point/20.48 μs. It has also been implemented on a high performance 0.13 μm, 1P8M CMOS process achieving a worst-case (0.9 V, 125 C) post-route clock frequency of 604.5 MHz and a sustained throughput of 4096 point/3.89 μs while consuming 4.4 W. The architecture is extended to accomplish FFT computations of 16K, 64K and 256K complex points with 352, 256 and 188 MHz operating frequencies respectively.

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An FFT Core for DVB‐T/DVB‐H Receivers

Cited by 17 publications

References 13 publications

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems

Fully Systolic FFT Architecture for Giga-sample Applications

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