This paper presents an environment for the automatic generation of FFT/IFFT cores. The cores are derived from a pipelined cascade architecture template supporting run-time programmable length, transform type selection and three different machine arithmetics (fixed-point, block floating-point and convergent block floating-point). The tool profiles arithmetics and generate the macrocell with the minimum operands bit-width (hence minimum circuit complexity) within the numerical accuracy budget given by the target application. Four case studies illustrate the use of the environment in multi-band OFDM communication systems (WLAN, xDSL, DVB-T/H and UWB). Implementation results of the generated macrocells are evaluated on a 65 nm CMOS standard cells library. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity (gate count, RAM/ROM bits) while keeping the same system level performance (throughput, transform size and numerical accuracy