Efficient Power Macromodeling Technique for IP-Based Digital System

Durrani, Yaseer Arafat; Abril, Ana; Riesgo, Teresa

doi:10.1109/iscas.2007.378252

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…Again, due to lack of recent work, the amount of references is found to be at minimum. In [10], the authors propose a High-Level power estimation model based on input signals statistics defined as: the input signal probability, the average input signal density and the spatial correlation. In their experiments, authors indicate an average error of 29.63% regarding power estimation.…”

Section: White/black-box Ipsmentioning

confidence: 99%

High-level power estimation techniques in embedded systems hardware: an overview

et al. 2022

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Power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited power budget systems (battery-operated hand-held devices, electro-optical pluggable modules, IoT and green energy systems, etc.). Subsequently, early power consumption estimation at design time is crucial for power optimization. The aim of this paper is to present an overview of High-Level power estimation techniques currently available along with a comprehensive comparison between different methodologies and their applications on estimated models. When high speed and high performance are key features of a specific embedded system, increase in energy consumption becomes the main hurdle to be tackled while keeping speed/performance v/s power consumption trade-off at a minimum. This paper provides designers, interested in power consumption modeling, with knowledge on how to select best power estimation techniques applied to designated target models.

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Section: White/black-box Ipsmentioning

confidence: 99%

High-level power estimation techniques in embedded systems hardware: an overview

et al. 2022

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Power estimation technique for DSP architectures

Durrani

Riesgo

2009

Digital Signal Processing

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ARTICLE INFO ABSTRACT Keywords:Macromodel DSP architecture Digital filter Power estimation Intellectual property Monte Cario simulationThe main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Cario zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estímate power dissipation of the system just by using the statistics of the macro-block's primary inputs.In experiments with the DSP system, the average error is 26%.

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Architectural power macromodeling technique for DSP architectures

Durrani

2009

2009 4th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscal Era

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Efficient Power Macromodeling Technique for IP-Based Digital System

Cited by 5 publications

References 11 publications

High-level power estimation techniques in embedded systems hardware: an overview

High-level power estimation techniques in embedded systems hardware: an overview

Power estimation technique for DSP architectures

Architectural power macromodeling technique for DSP architectures

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