Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)
DOI: 10.1109/apasic.2000.896965
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Efficient random vector verification method for an embedded 32-bit RISC core

Abstract: Processors require both intensive and extensive functional verification in their design phase to satisb their general purposability. The proposed random vector verification method for CalmRISCTM-32 core meets this goal by contributing complementary assistance for conventional verification methods. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors ifany difference is found between them. These processes are aut… Show more

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