Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic

Abstract

In this paper we present different optimization techniques on look-up table based algorithms for double precision floating point arithmetic. Based on our analysis of different look-up table based algorithms in the literature, we re-engineer basics blocks of the algorithms (i.e. multiplier(s) and adder(s)) to facilitate area and timing benefits to achieve higher performance. We propose different look-up table optimization techniques for the algorithms. We also analyze trade-off in employing exact rounding (0.5ulp) (unit in the last place) in the double precision floating point unit. Based on performance and extensibility criteria we take algorithms proposed by Wong and Goto as a base case to validate our optimization techniques and compare the performance with other algorithms in the literature. We improve the performance (latency × area) of Wong and Goto division algorithm by 26.94%.

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

“…FPS has several resources to perform computations. In this exposition, we use carefully designed DOT4, a square root, and a divider for realization of DGEQR2, DGEQRF, DGEQR2HT, and DGEQRFHT routines [21] [22]. Logical place of arithmetic units is shown in the figure 12 and structure of DOT4 is shown in figure 13.…”

“…We show that sequential realization in PE and parallel realization of GGR based QR factorization in REDEFINE are scalable. Furthermore, it is shown that the speed-up in parallel realization in REDEFINE over sequential realization in PE is commensurate with the hardware resources employed in REDEFINE and the speed-up asymptotically approaches theoretical peak of REDEFINE CGRA For our implementations in PE and REDEFINE, we have used double precision Floating Point Unit (FPU) presented in [14] with recommendations presented in [15]. Organization of the papers is as follows: In section 2, we discuss about CGR, REDEFINE and some of the FPGA, multicore, and GPGPU based realizations of QR factorization.…”

“…Realization of MHT, outperforms realization of DGEMM as shown in figure 14(d). We also show scalability of our solution by attaching PE as a CFU in REDEFINE Due to availability of double precision floating point arithmetic unites like adder, multiplier, square root, and divider, we emphasize on the realization of DGEQR2, and DGEQRF using HT and MHT [21] [22]. Organization of the paper is as follows: In section 2, we briefly discuss about REDEFINE and some of the recent realization of QR factorization.…”

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design

“…For our experiments, we use Processing Element (PE) design presented in [9]. We optimize Floating Point Unit (FPU) design presented in [13] with recommendations presented in [12] for optimum Instructions Per Cycle (IPC). The paper is organized as follows: In section 2, MFA, KF and REDEFINE are discussed.…”

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design

“…Major reason for centralization of efforts toward software optimizations and efficient exploitation of memory hierarchy is mainly due to several architectural parameters that are not in the control of programmer [16]. For example, the depth of the pipeline (pipeline stages) in the underlying platform [17]. In this paper, we present a theoretical framework that assists in establishing a relation between pipeline depth of different floating point operations with size and type of the workload.…”