Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis

Abstract

- I.INTRODUCTIONAs we move towards the 32nm and lower device feature sizes, process variations are becoming an ever increasing concern for the design of high performance integrated circuits [1]. The process variations can cause excessive uncertainty in timing calculation, which in turn calls for sophisticated analysis techniques to reduce the uncertainty. As the number of variation sources increases, corner-based static timing analysis (STA) techniques become computationally very expensive. Moreover, with the decreasing size of transistors and interconnect width, the variation of electrical characteristics of logic cells and onchip wires is getting proportionally higher. Delay and slew based library cell modeling methodology is not adequate for the new nanometer-era CMOS technologies any more. This is due in part to the highly nonlinear response behavior of devices and interconnections in deep submicron regimes. Current Source Modeling (CSM) has been introduced as an alternative analysis approach for accurate delay modeling in such regimes [3]- [5]. To maintain some compatibility with standard flows and tools, ECSM [6] (proposed by Cadence Design Systems), and CCS [7] (developed by Synopsys) are extensions of the Liberty library format. CSM modeling needs the storage of tables of current or voltage waveforms. Moreover, timing analysis requires a library characterization with more points in the process, voltage, and temperature (PVT) space so as to handle static and dynamic variations in device and interconnect behavior. A complete set of waveform-based library characterization data for different PVT variables and for timing, noise and power analyses would result in an explosion of the library modeling data.To address this data explosion problem, a compact variational model waveform was presented in [8], which stores only the nominal waveforms, yet it allows the analysis tools to produce any perturbed waveform by using appropriate time/voltage shift or scale operations. This is a step in the right direction; but unfortunately it does not solve the problem i.e., the proposed method still requires large memory footprint to store the nominal waveforms. The Singular Value Decomposition (SVD) algorithm proposed in [9] solves the latter problem by modeling the voltage waveforms of the logic cells as a linear combination of a fixed set of basis waveforms. Reference [10] addresses adaptive compaction of current-source model libraries by representing each waveform using a variable number of basis waveforms, i.e. using 2-3 basis waveforms to represent a large subset of waveforms and using up to 14 basis waveforms for a small subset of waveforms. The method results in one to two orders of magnitude reduction in the size of the stored characterization data. The present paper extends [10] to handle variational waveforms for statistical static timing analysis (SSTA). Additionally it presents a mathematical foundation to relate the accuracy of compressed data in the reduced space to that in the uncompressed space. I...

CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach

“…The values of these components can be characterized using HSPICE simulations. The CSM components of a logic cell can be stored in LUTs and utilized for noise, timing and power analysis of VLSI circuits [11], [14], [15], [18]. Fig.…”