Efficient Retiming of Multirate DSP Algorithms

Zhu, Xun; Basten, Twan; Geilen, Marc; Stuijk, Sander

doi:10.1109/tcad.2011.2182352

Cited by 21 publications

(3 citation statements)

References 22 publications

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“…Xue-Yang Zhu et al [1] introduced new methods for finding a feasible retiming and an optimal retiming so that a Signal Data Flow Graph (SDFG) achieves its smallest iteration period. Xue-Yang Zhu [3] examined the relationship between SDFG and its equivalent Homogeneous Signal Data Flow Graph(HSDFG), and proved some useful properties by which iteration period can be computed directly on SDFGs.…”

Section: Related Workmentioning

confidence: 99%

Performance enhancement of multirate digital filter structures using advanced DSP optimization techniques

Gawande¹,

Metkar²,

Khanchandani³

2015

2015 International Conference on Information Processing (ICIP)

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A frequent task in digital signal processing is to adjust the sampling rate according to the signal of interest. Systems with different sampling rates are referred to as multirate systems. There is a huge scope to optimize the Multirate filters. There are various advanced digital signal processing techniques such as Retiming, Parallel processing, Pipelining, Folding, Unfolding available to optimize multirate digital filters. In this paper, we introduced different multirate filter structures using various optimization techniques which results in high speed, high throughput and high computation rate. Multirate filter structures are implemented for decimation using Xilinx System Generator to target spartan-6 xc6slx150T-4fgg676 Field Programmable Gate Array device. The best decimation filter structure among the compared structures is Transposed Pipelined which gives improvement in speed almost by 100MHz for the selected filter specifications. The optimized structure also yields higher throughput and computation rate compared to other structures used for decimation in this paper.

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Section: Related Workmentioning

confidence: 99%

Performance enhancement of multirate digital filter structures using advanced DSP optimization techniques

Gawande¹,

Metkar²,

Khanchandani³

2015

2015 International Conference on Information Processing (ICIP)

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“…Filters are used in audio processing, speech processing (detection, compression, and reconstruction), modems, motor control algorithms, video and image processing, and so forth. Retiming is important step [10] in high level synthesis (HLS) of digital filters. HLS is nothing but to map behavioural descriptions of algorithms to physical realizations.…”

Section: Data Flow Graphs (Dfgs)mentioning

confidence: 99%

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Yagain

Krishna

2014

VLSI Design

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

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“…Retiming an actor once means firing the actor once. Retiming may reduce the IP of static periodic schedules of an SDFG [10]. Consider the HSDFG G 0 in Fig.…”

Section: Introductionmentioning

confidence: 99%

Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding

Zhu

Geilen

Basten

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Synchronous dataflow graphs (SDFGs) are widely used to represent DSP algorithms and streaming media applications. This paper presents several methods for binding and scheduling SDFGs on a multiprocessor platform. Exploring the state-space generated by a self-timed execution (STE) of an SDFG, we present an exact method for static rate-optimal scheduling of SDFGs via implicit retiming and unfolding. By modeling a constraint as an extra enabling condition for the STE, we get a constrained STE which implies a schedule under the constraint. We present a general framework for scheduling SDFGs under constraints on the number of processors, buffer sizes, auto-concurrency, or combinations of them. Exploring the state-space generated by the constrained STE, we can check whether a retiming, which leads to a rate-optimal schedule under the processor (or memory) constraint, exists. Combining this with a binary search strategy, we present heuristic methods to find a proper retiming and a static scheduling that schedules the retimed SDFG with optimal rate and with as few processors (or as little storage space) as possible. None of the methods explicitly converts an SDFG to its equivalent homogenous SDFG, the size of which may be tremendously larger than the original SDFG. We perform experiments on several models of real applications and hundreds of synthetic SDFGs. The results show that the exact method outperforms existing methods significantly; our heuristics reduce the resources used and are computationally efficient.

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Efficient Retiming of Multirate DSP Algorithms

Cited by 21 publications

References 22 publications

Performance enhancement of multirate digital filter structures using advanced DSP optimization techniques

Performance enhancement of multirate digital filter structures using advanced DSP optimization techniques

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding

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