Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014 2014
DOI: 10.7873/date.2014.138
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Efficient SMT-based ATPG for interconnect open defects

Abstract: Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. This paper presents a n… Show more

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Cited by 7 publications
(2 citation statements)
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“…If some aggressor is influenced by the value of the victim line, oscillations may arise [2]. In this regards, the test generation method proposed in [10] makes use of a satisfiability modulo theory (SMT) solver engine to accurately model the effects of charge partition between the victim and the aggressor lines. This ATPG, may generate test vectors resulting in oscillations, but it does not consider the specific problems related to the propagation of such values.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…If some aggressor is influenced by the value of the victim line, oscillations may arise [2]. In this regards, the test generation method proposed in [10] makes use of a satisfiability modulo theory (SMT) solver engine to accurately model the effects of charge partition between the victim and the aggressor lines. This ATPG, may generate test vectors resulting in oscillations, but it does not consider the specific problems related to the propagation of such values.…”
Section: Introductionmentioning
confidence: 99%
“…These reasons motivated the development of ATPG strategies targeting the detection of oscillating FBFs and easily extendable to other faults that shows an oscillating behavior. To this purpose, we exploit Boolean satisfiabilitybased (SAT) test-generation techniques [11] that have been shown to be capable of handling large circuits [12] for a wide variety of fault models including: 1) stuck-at faults [11], [12], [13]; 2) bridging faults [8], [14]; 3) open faults [10]; 4) delay faults [15], [16].…”
Section: Introductionmentioning
confidence: 99%