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The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output\ud conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality\ud of fault simulation and test generation tools using nominal IC parameters, we studied BF detection\ud as a function of the standard deviation of parameters: results show that a single test vector cannot\ud ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing\ud null escape probability is upper-bounded with respect to variations of parameters, as verified by\ud Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for\ud low frequency testing. A fault simulator and a test generator have been developed supporting the\ud search of minimal test sets targeting a null escape probability

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One key issue in design flows based on reuse of third-party intellectual property (IP) components is the need to estimate the impact of component instantiation within complex designs. In this paper we introduce JavaCAD, an internetbased EDA tool built on a secure client-server architecture that enables designers to perform simulation and cost estimation of circuits containing IP components wihout actually purchasing them. At the same time, the tool ensures intellectual property protection for the vendors of IP components, and for the IP-users as well. Moreover, JavaCAD supports negotiation of the amount of information and the accuracy of cost estimates, thereby providing seamless transition between IP evaluation and purchase.