Specification and validation of distributed IP-based designs with JavaCAD

Dalpasso, M.; Bogliolo, Alessandro; Benini, Luca

doi:10.1109/date.1999.761203

Cited by 13 publications

(17 citation statements)

References 11 publications

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“…functionalities, testa- bility, performances, have to be evaluated before including it into the final design. Previously defined techniques [2,6,7,9] present alternative methodologies for allowing a design team to evaluate different IPs integrations into the final design without violating the IPs of the core provider. The goal of the technique presented in this paper is to integrate these functionality evaluation methodologies with a testability evaluation framework.…”

Section: Introductionmentioning

confidence: 99%

Protected IP-core test generation

Fin¹,

Fummi²

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. IPs are usually provided with their own test patterns that can be used only by applying design for testability techniques onto the chip. Whenever physical faults must be detected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test generation on faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. Finally, remote simulation can be also performed locally to avoid bandwidth bottleneck and the test generation process can be indifferently applied at lower abstraction levels such as RT and gate.

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Section: Introductionmentioning

confidence: 99%

Protected IP-core test generation

Fin¹,

Fummi²

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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“…The need of run-time communication between designers and providers was addressed by JavaCAD [1] to enable context-dependent dynamic estimation of traditional cost metrics, with improvements upon the accuracy provided by context-independent static estimators. Within JavaCAD, boundary information (e.g., input patterns/statistics and output loads) are automatically collected for each IP component during functional simulation of the entire design and sent to the providers to allow instance-dependent low-level estimation of the cost metrics of interest [2].…”

Section: Virtual Fault Simulationmentioning

confidence: 99%

“…Internet connectivity is gaining increasing importance in electronic design automation [8,9,10,11,12,13]: it offers new opportunities for remote tool integration, it enables new ways of information sharing and collaborative design, and it enhances the market penetration of IP components. The JavaCAD design framework has been developed to provide support for distributed IP-based design [1,2], and it has been extended in this work to implement virtual fault simulation.…”

Section: Introductionmentioning

confidence: 99%

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Virtual fault simulation of distributed IP-based designs

Dalpasso¹,

Bogliolo²,

Benini³

et al.

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)

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Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design [1,2]. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.

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“…For example, when using Java as simulation language [1], IP components can stay at the providers site and simulation can be performed via the Internet. Although such an approach is interesting and very safe, it suffers from the dependency on the network in terms of availability and transfer speed.…”

Section: A Related Workmentioning

confidence: 99%

Reuse and protection of intellectual property in the SpecC system

Domer¹,

Gajski²

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Abstract-In system-level design, the key to cope with the complexities involved with System-on-Chip (SOC) designs, is the reuse of Intellectual Property (IP). With the increasing demand for IP, the mechanism to protect an IP component from being copied, modified, or reverse-engineered, becomes very important. This paper describes how reuse and protection of IP is supported by the SpecC language and the SpecC design environment.

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Specification and validation of distributed IP-based designs with JavaCAD

Cited by 13 publications

References 11 publications

Protected IP-core test generation

Protected IP-core test generation

Virtual fault simulation of distributed IP-based designs

Reuse and protection of intellectual property in the SpecC system

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