High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

Favalli, M.; Dalpasso, M.

doi:10.1109/dft.2007.19

Cited by 5 publications

(14 citation statements)

References 6 publications

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“…In testing for static defects, process variation has been considered in testing analog devices [154], and testing for bridges in static CMOS designs [99,155]. Testing analog devices under process variation means that the stimuli used for nominal values of IC parameters are not necessarily effective for all configurations of IC parameters as they occur due to variation.…”

Section: Logic Testing Under Process Variationmentioning

confidence: 99%

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Logic Testing Under Process Variationmentioning

confidence: 99%

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…The detection of a target delay fault by a single test vector pair occurs with a certain delay fault detection probability, which must be increased by the application of additional test vector pairs to minimize the risk of test escapes [6]. This probability depends on many delay test parameters [7]- [13], which must be optimized to find a suitable compromise between the final delay test quality and the test cost.…”

Section: Introductionmentioning

confidence: 99%

Incremental computation of delay fault detection probability for variation-aware test generation

Wagner

Wunderlich

2014

2014 19th IEEE European Test Symposium (ETS)

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Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead.To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.

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“…Two experiments were performed. In the first experiment (Table III columns [8][9][10][11][12][13] we kept the original test set of each circuit and augmented it with additional test patterns to reduce test escapes for three weighted average test robustness targets (W A target 0.96, 0.98 and 0.995). Columns marked "WA" show the weighted average robustness of the test sets, evaluated with other PVCs than those that were used in test generation.…”

Section: B Test Quality Gain Through Process Variation-aware Atpgmentioning

confidence: 99%

“…The results show that test sets generated without consideration of process variation are compromised in terms of test quality in the presence of process variation. To regain the lost test quality, additional test patterns can be generated (Table III column [8][9][10][11][12][13]. Alternatively, high test quality in the presence of process variation can be obtained by generating a new test set (Table III column [14][15][16][17][18][19].…”

Section: B Test Quality Gain Through Process Variation-aware Atpgmentioning

confidence: 99%

“…This paper addresses the impact of process variation on static defects with focus on resistive bridging faults. In [7], [8] it was shown that tests for bridging faults can be generated such that they are valid independent of process variation. However, these tests may include many test patterns that do not contribute to detecting unique bridge resistance ranges, leading to an unnecessarily large test set.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Process Variation-Aware Test for Resistive Bridges

Ingelsson

Al-Hashimi

Khursheed

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

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High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

Cited by 5 publications

References 6 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

Incremental computation of delay fault detection probability for variation-aware test generation

Process Variation-Aware Test for Resistive Bridges

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