Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors

Touati, Sid; Brault, Frederic; Deschinkel, Karine; Dinechin, Benoît Dupont de

doi:10.1145/2043662.2043671

Cited by 3 publications

(12 citation statements)

References 24 publications

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“…They are used inside a framework called SIRA [23,24]. Unlike the previous approaches for periodic register allocation, reuse graphs are used before software pipelining to generate a move-free or a spill-free periodic register allocation in the presence of multiple register types.…”

Section: Sira and Reuse Graphsmentioning

confidence: 99%

“…A simple way to explain SIRA is to provide an example. All the theory has already been presented in Touati and Eisenbeis [24], and we recently showed that optimising the register requirement for multiple register types in one go is a better approach than optimising for every register type separately [23]. Figure 5(a) provides an initial DDG with two register types t 1 and t 2 .…”

Section: Sira and Reuse Graphsmentioning

confidence: 99%

“…These constraints have been defined in [24,23], that we summarise here. The proof is organised in three subsections.…”

Section: Proofmentioning

confidence: 99%

“…A recent description for multiple register types can be found in Touati et al [23,24]. We say that a value is killed when all its consumers have already read it, and consequently, it does not have to occupy a register anymore.…”

Section: Linear Constraints For ν Variablesmentioning

confidence: 99%

“…classes). On such architectures, state-of-the-art algorithms [10,24] compute the sufficient unrolling degree, i.e., the unrolling degree that should be applied to a loop so that it is always possible to allocate the variables of each register type with a minimal number of registers. This article demonstrates that minimising the unroll factor on each register type separately does not define a global minimal unroll factor, and we provide an appropriate problem definition and an algorithmic solution in this context.…”

Section: Introductionmentioning

confidence: 99%

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Minimal Unroll Factor for Code Generation of Software Pipelining

Bachir

Touati

Brault

et al. 2012

Int J Parallel Prog

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International audienceWe address the problem of generating compact code from software pipelined loops. Although software pipelining is a powerful technique to extract fine- grain parallelism, it generates lifetime intervals spanning multiple loop iterations. These intervals require periodic register allocation (also called variable expansion), which in turn yields a code generation challenge. We are looking for the minimal unrolling factor enabling the periodic register allocation of software pipelined kernels. This challenge is generally addressed through one of: (1) hardware support in the form of rotating register files, which solve the unrolling problem but are expensive in hard- ware; (2) register renaming by inserting register moves, which increase the number of operations in the loop, and may damage the schedule of the software pipeline and reduce throughput; (3) post-pass loop unrolling that does not compromise throughput but often leads to impractical code growth. The latter approach relies on the proof that MAXLIVE registers (maximal number of values simultaneously alive) are sufficient for periodic register allocation (Eisenbeis et al. in PACT '95: Proceedings of the IFIP WG10.3 working conference on Parallel Architectures and Compilation Techniques, pages 264-267, Manchester, UK, 1995; Hendren et al. in CC '92: Proceedings of the 4th International Conference on Compiler Construction, pages 176-191, London, UK, 1992). However, the best existing heuristic for controlling this code growth--modulo variable expansion (Lam in SIGPLAN Not 23(7):318-328, 1988)--may not apply the correct amount of loop unrolling to guarantee that MAXLIVE registers are enough, which may result in register spills Eisenbeis et al. in PACT '95: Proceedings of the IFIP WG10.3 working conference on Parallel Architectures and Compilation Techniques, pages 264-267, Manchester, UK, 1995. This paper presents our research results on the open problem of minimal loop unrolling, allowing a software-only code generation M. Bachir * S.-A.-A. Touati (B) * F. Brault * D. Gregg * A. Cohen University of Nice Sophia-Antipolis, Nice, France e-mail: Sid.Touati@inria.fr 123 that does not trade the optimality of the initiation interval ( I I ) for the compactness of the generated code. Our novel idea is to use the remaining free registers after periodic register allocation to relax the constraints on register reuse. The problem of minimal loop unrolling arises either before or after software pipelining, either with a single or with multiple register types (classes). We provide a formal problem definition for each scenario, and we propose and study a dedicated algorithm for each problem. Our solu- tions are implemented within an industrial-strength compiler for a VLIW embedded processor from STMicroelectronics, and validated on multiple benchmarks suites

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Section: Sira and Reuse Graphsmentioning

confidence: 99%

Section: Sira and Reuse Graphsmentioning

confidence: 99%

“…These constraints have been defined in [24,23], that we summarise here. The proof is organised in three subsections.…”

Section: Proofmentioning

confidence: 99%

Section: Linear Constraints For ν Variablesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Minimal Unroll Factor for Code Generation of Software Pipelining

Bachir

Touati

Brault

et al. 2012

Int J Parallel Prog

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Bibliography

2014

Advanced Backend Code Optimization

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How to eliminate non-positive circuits in periodic scheduling: a proactive strategy based on shortest path equations

Touati¹,

Briais

Deschinkel

2013

RAIRO-Oper. Res.

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Usual periodic scheduling problems deal with precedence constraints having non-negative latencies. This seems a natural way for modelling scheduling problems, since task delays are generally nonnegative quantities. However, in some cases, we need to consider edges latencies that do not only model task latencies, but model other precedence constraints. For instance in register optimisation problems devoted to optimising compilation, a generic machine or processor model can allow considering access delays into/from registers. Edge latencies may be then non-positive leading to a difficult scheduling problem in presence of resources constraints. This research result is related to the problem of periodic scheduling with storage requirement optimisation; its aims is to solve the practical problem of register optimisation in optimising compilation. We show that pre-conditioning a data dependence graph (DDG) to satisfy register constraints before periodic scheduling under resources constraints may create circuits with non-positive distances, resulted from the acceptance of non-positive edge latencies. As a compiler construction strategy, it is forbidden to allow the creation of circuits with non-positive distances during the compilation flow, because such DDG circuits do not guarantee the existence of a valid instruction schedule under resource constraints. We study two solutions to avoid the creation of these problematic circuits. A first solution is reactive, it tolerates the creation of non-positive circuit in a first step, and if detected in a further check step, makes a backtrack to eliminate them. A second solution is proactive, it prevents the creation of non-positive circuits in the DDG during the register optimisation process. It is based on shortest path equations which define a necessary and sufficient condition to free any DDG from these problematic circuits. Then we deduce a linear program accordingly. We have implemented our solutions and we present successful experimental results.Register optimisation is a broad research topic in optimising compilation since long time. We must distinguish three possible phase orderings between register optimisation and instruction scheduling:1. Register constraints are handled after instruction scheduling. This topic is called register allocation, and is well studied mathematically in [1-3] for acyclic

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Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors

Cited by 3 publications

References 24 publications

Minimal Unroll Factor for Code Generation of Software Pipelining

Minimal Unroll Factor for Code Generation of Software Pipelining

Bibliography

How to eliminate non-positive circuits in periodic scheduling: a proactive strategy based on shortest path equations

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