SID-AHMED-ALI TOUATI, University of Versailles Saint-Quentin-en-Yvelines FREDERIC BRAULT, INRIA-Saclay KARINE DESCHINKEL, University of Versailles Saint-Quentin-en-Yvelines BENOÎT DUPONT DE DINECHIN, STMicroelectronicsIntegrating register allocation and software pipelining of loops is an active research area. We focus on techniques that precondition the dependence graph before software pipelining in order to ensure that no register spill instructions are inserted by the register allocator in the software pipelined loop. If spilling is not necessary for the input code, preconditioning techniques insert dependence arcs so that the maximum register pressure MAXLIVE achieved by any loop schedule is below the number of available registers, without hurting the initiation interval if possible. When a solution exists, a spill-free software pipeline is guaranteed to exist.Existing preconditioning techniques consider one register type (register class) at a time [Deschinkel and Touati 2008]. In this article, we extend preconditioning techniques so that multiple register types are considered simultaneously. First, we generalize the existing theory of register pressure minimization for cyclic scheduling. Second, we implement our method inside the production compiler of the ST2xx VLIW family, and we demonstrate its efficiency on industry benchmarks (FFMPEG, MEDIABENCH, SPEC2000, SPEC2006). We demonstrate a high spill reduction rate without a significant initiation interval loss.

The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging. Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs. A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to address die fracture from both the front and the back sides of the wafer, yielding an authentic 3D approach to crack-stop.

This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed ‡ .

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