Single-pass frame generation for multi-layer 3D circuits

Abstract

This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed ‡ .

Minimizing die fracture in 3DIC die integration

“…As described by Brault et al., 32 a dedicated frame generation tool can be used to build overlapping frames simultaneously. In our case, three different frames are generated, considering all the intra-constraints and inter-constraints between the objects to be placed on the two sides of the top wafer and on the upper side of the bottom wafer.…”

Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns

“…As described by Brault et al, 11 a dedicated frame generation tool can be used to build the two frames at once. It will take into account all the intra-constraints and inter-constraints between the objects to be placed on the two sides of the wafer.…”