Efficient Temperature Sensor Based on SOI Gate-All-Around Electrostatically Formed Nanowire Transistor

Effective uncooled infrared bolometer based on SOI gate all around electrostatically formed nanowire transistors

“…The n-type transistor layer includes Arsenic doping (7×10 19 cm −3 ) for the N + source/ drain regions, and Boron doping (2×10 20 cm −3 ) for the two lateral P + -N − junction gates (JG). The channel region has vertical gradient n-type doping, ranging from 4.8×10 17 to 1.7×10 17 cm −3 [6,7]. The length of the transistor including the contacts is L=1.6 μm, and the width is W=0.8 μm, where the channel region has a length of 1 μm, and width of 0.25 μm.…”

“…The 3D nanometer scaling of the single EFN device channel is performed electrostatically post fabrication (down to a ∼6 nm diameter) by negative voltage biases applied to the side gates (JG), back gate (BG), and top gate (TG) [7,8]. This method is also used to tune the device channel vertical position to the DAA mode, where the SOI GAA EFN transistor operates effectively.…”

“…In the DAA mode, the conducting channel is moved away from the top silicon surface and is tens to several nanometers in size. Figure 1(c) shows a cross section view of the transistor in the micro-bolometer pixel operated in DAA mode, where high temperature sensitivity (TCC=13.3%/K) with I DS ≈20 pA at V DS =0.1 V and low noise level are reached (figures 2, 3, and [7]). This is due to the improved electrostatic integrity (improved SS, gm JG , V TH (JG)) obtained using SOI EFN transistor with an additional top gate electrode compare to conventional SOI EFN transistor and planar SOI MOSFETs with an inverted channel formed at the top surface of the SOI layer.…”

“…The TCC's of the device were calculated from the measurements of I DS -V TG at various V JG 's. The measured TCC's compared with the simulations from previous work [7]. These simulations with large amount of data points were used in further calculations of the device responsivity, noise equivalent power, and noise equivalent temperature difference.…”

“…Similar to NEP values at V TG <−0.4 V for V JG =−0.5 V, the NETD's changes ∼4.0-5.7×10 5 K are large, which is impractical for thermal sensing applications. Therefore, the off-state regime of the SOI GAA EFN transistor where the front surface is in inversion is not desired, despite the high TCC's of 7%-10%/K simulated in [7].…”