EGRA: A Coarse Grained Reconfigurable Architectural Template

Ansaloni, Giovanni; Bonzini, Paolo; Pozzi, Laura

doi:10.1109/tvlsi.2010.2044667

Cited by 78 publications

(24 citation statements)

References 21 publications

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“…Multiple operations can be cyclically performed providing a set configuration words for each RC, and activating the proper one during execution [1]. Figure 1 provides a high-level view of the envisaged CGRA mesh.…”

Section: Shared Cgra Acceleratormentioning

confidence: 99%

A multi-core reconfigurable architecture for ultra-low power bio-signal analysis

Duch

Basu

Braojos

et al. 2016

2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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Abstract-This paper introduces a novel computing architecture devoted to the ultra-low power analysis of multiple biosignals. Its structure comprises several processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable Array (CGRA). The CGRA supports the efficient execution of the computationally intensive kernels present in this application domain, while requiring a low reconfiguration overhead. The run-time behavior of the resulting heterogeneous system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors and regulates access to the reconfigurable accelerator. The architecture achieves speed-ups of up to 11x on different bio-signal processing kernels and system-level energy savings of up to 18.6%, with respect to a multi-core platform, which does not feature CGRA acceleration.

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Section: Shared Cgra Acceleratormentioning

confidence: 99%

A multi-core reconfigurable architecture for ultra-low power bio-signal analysis

Duch

Basu

Braojos

et al. 2016

2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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“…Many CGRAs were proposed in last decades, such as MorphoSys [8], RaPiD [9], PipeRench [10], EGRA [11]. Efficiently mapping H.264/AVC decoder onto a flexible platform presents a big challenge to existing architectures and design methodology.…”

Section: Related Workmentioning

confidence: 99%

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Liu

Chen

Cao

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and dataintensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the offchip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm 2 silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.

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“…In this paper, an instance of the EGRA is considered. The template is briefly introduced here; more details on its structure are provided in [33]. Fig.…”

Section: Target Architecturementioning

confidence: 99%

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Ansaloni

Tanimura

Pozzi

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than stateof-the-art approaches (as much as 38% for the benchmark applications considered).

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EGRA: A Coarse Grained Reconfigurable Architectural Template

Cited by 78 publications

References 21 publications

A multi-core reconfigurable architecture for ultra-low power bio-signal analysis

A multi-core reconfigurable architecture for ultra-low power bio-signal analysis

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

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