Electric-field-related reliability of AlGaAs/GaAs power HFETs: bias dependence and correlation with breakdown

Abstract

This work shows experimental and simulated data of hot electron degradation of power AlGaAs/GaAs HFETs with different gate lengths and recess widths, and uses them to infer general indications on the bias and geometry dependence of the device high-field degradation, the meaningfulness of the breakdown voltage figure of merit from a reliability standpoint, and the physical phenomena taking place in the devices during the stress and leading to performance degradation. Possible formulations of a voltage-acceleration law for lifetime extrapolation are also tested.

A complete RF power technology assessment for military applications

“…Concerning the results obtained after each step stress or each test file, all the key parameters (Idss, Gm, Vp, Pout) degradations were lower than 6% in every test scheme (see table 3), and we could even Table 3 Complete results Ref a b c d e f g Idss -4% -3% -2% -3% -3% -6% +6% Gm +4% +6% +2% ≈ +1% +3% -1% Vp -6% -7% ≈ -3% -4% -4% +5% observe a slight increase for Pout around 2 % in some cases. The observed evolutions did not seem to be thermally activated (see figures 7 and 8), the slopes were almost the same at -40°C or +83°C and did not reveal a square-law time dependence of Ids degradation as described by Dieci [13] or a log time dependence [6] but rather a linear one.…”

A review of the use of electro-thermal simulations for the analysis of heterostructure FETs

“…The 3D simulation volume is shown in Fig. 14. Assuming a 200-lm-wide HFET, such as those studied here [9], the symmetry of the structure allows limiting the analysis to one half (the 100 lm top contact of Fig. 14), if we replace the plane of symmetry with an adiabatic sidewall.…”

“…The device is an Al 0.25 Ga 0.75 As/GaAs medium-power HFETs fabricated by Alenia-Marconi Systems [9]. It has a 200 lm gate width and a gate length of 0.25 lm.…”

Analysis of the gate current as a suitable indicator for FET degradation under nonlinear dynamic regime

“…A nonlinear model allows simulating the device behavior under the actual operating conditions (i.e., nonlinear dynamic operation) that are defined by the specific circuit considered (e.g., amplifier, mixer, oscillator). However, when electron devices are subject to degradation [4][5][6] during their operating life, this inevitably leads to a degradation of circuit performance. As a consequence, device and circuit performance during operating life may become increasingly different from the one predicted by the nonlinear model identified on the basis of measurements carried out on the ''fresh" (i.e., not stressed) device.…”

“…As a matter of fact, microwave FET device degradation has been extensively studied under static device operation [4,5], which is extremely different from the actual device operation. The reasons for such a choice are multiple: (I) DC experiments are simpler and allow for easier identification of accelerated stressing conditions, thus avoiding the complexity of large-signal high-frequency measurement setups [7]; (II) also from the standpoint of numerical simulation and modeling in general, nonlinear dynamic operation is quite unpractical both for complexity and simulation time.…”