Electrical Activity of Dislocations and Defects in Strained Si and Ge Based Devices

Wang

et al. 2010

J. Electrochem. Soc.

Extended-defect aspects of state-of-the-art Ge-on-Si materials and devices are discussed with an emphasis on the impact of postgrowth thermal budget on the structural and electrical epilayer characteristics. The observations on the annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations ͑TDs͒. For the present processing conditions, the leakage current of Ge complementary metal oxide semiconductor compatible p + n junctions becomes independent of the TD density at about 10 7 cm −2 . © 2009 The Electrochemical Society. ͓DOI: 10.1149/1.3267514͔ All rights reserved. Defect engineering is a common practice in silicon-based integrated circuit and solar cell technology and has been extensively investigated during the past 2 decades, leading to its successful implementation in manufacturing lines. In addition, for sub-45 nm technologies, strain engineering is required to boost the device performance in agreement with the International Technology Roadmap for Semiconductors. In recent years, strong research efforts have also been focusing on the use of Ge-based channels for the sub-22 nm complementary metal oxide semiconductor ͑CMOS͒ node, 1 whereby epitaxial Ge-on-Si has a very strong potential. This also opens the door to achieve a full monolithic integration of Ge and III-V materials on a silicon substrate, leading to system-on-chip applications. The main challenge of the epitaxial deposition of Ge on Si is the 4% lattice mismatch and the difference in thermal expansion coefficient, which readily leads to the buildup of mechanical stress and, subsequently, its relaxation by the generation of misfit and threading dislocations ͑TDs͒.2,3 Therefore, the control of misfit and TDs during both substrate preparation and device processing is a must to arrive at a good-yielding, high performing technology. The aim of this paper is to summarize our recent developments in Geon-Si materials and devices and to address the remaining challenges. An extensive overview of the foregoing work can be found in Chap. 4 of Ref. 4.The focus in this work is on the defect formation and control during the fabrication of Ge virtual substrates on silicon by chemical vapor deposition. Hereby, several approaches can be followed 2-4 to optimize the threading dislocation density ͑TDD͒ either by the use of a relaxed SiGe-graded buffer layer or by the direct deposition of a thick Ge epitaxial layer on silicon. Three different cases are considered, whereby the impact of a postgrowth ͑PG͒ anneal on the TDD is highlighted, and the impact on the electrical device performance is mainly evaluated through the leakage current of p + n junctions fabricated in these layers. The procedures to separate the area from the perimeter leakage current have been outlined previously. 5,6 It is demonstrated that a PG anneal or thermal budget may have both beneficial and detrimental effects, depending on the application and type of layer. For a relaxed virtual Ge substrate, the PG anneali...

Section: Thick Relaxed Epitaxial Ge Layersmentioning

confidence: 69%

Section: Thin Strained Epitaxial Ge Layersmentioning

confidence: 99%

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Wang

et al. 2010

J. Electrochem. Soc.

“…Concerning the leakage current of junctions processed in these layers one can distinguish between three different regimes, depending on the stress in the layer. 58 For fully strained layers, the leakage current is independent of the layer thickness and will exponentially increase with the Ge content in the SiGe layer. This is due to the smaller bandgap and corresponding higher n i for increasing Ge content.…”

Section: Strained Si Layers On a Strain Relaxed Sige Buffer Layer-str...mentioning

confidence: 99%

Review—Device Assessment of Electrically Active Defects in High-Mobility Materials

Claeys

Simoen

ECS J. Solid State Sci. Technol.

et al. 2016

The stringent device performance specifications of advanced scaled down technologies necessitates the implementation of high mobility substrates such as SiGe, Strained Si (sSi), Ge, sGe and/or III-V materials like GaAs, InGaAs. The control of the stress-induced defects remains a key challenge. Simple device structures such as capacitors, diodes and transistors are used to assess the electrical activity of extended defects (dislocations; antiphase boundaries; …) in high-mobility channel materials. Beside junction current analyses and lifetime studies, also the use of low-frequency noise characterization is reported. Special case studies are discussed to illustrate the used methodology. The potential of TCAD studies to better understand the electrical defect activity is also briefly addressed.

“…It has recently been shown that there exists a clear correlation between the TD density and the electrical performance of SiGe structures such as junction leakage current and carrier lifetime. 4,5 Recessed SiGe S/D structures in combination with a high-gate dielectric also lead to a higher low-frequency noise level. 6,7 For advanced p-channel metal oxide semiconductor field effect transistors ͑pMOSFETs͒, a suitable technique to enhance the hole channel mobility is by replacing the silicon source/drain ͑S/D͒ regions by SiGe ones.…”

mentioning

confidence: 99%

Leakage Current Control in Recessed SiGe Source/Drain Junctions

Claeys

González

et al. 2007

J. Electrochem. Soc.

The impact of different process parameters, namely, the trench etch depth, the total epitaxial SiGe thickness, and the epi elevation, on the leakage current of recessed Si 0.8 Ge 0.2 source/drain junctions has been systematically investigated. Besides the behavior of the forward and the reverse currents, attention is also given to the temperature dependence of the leakage current. It is found that both the bulk and the peripheral leakage current density increase strongly with increasing etch depth. Empirically, an exponential dependence has been observed between the area leakage current density at Ϫ1 V and the distance d j between the Si 0.8 Ge 0.2 -Si interface and the electrical p-n junction, whereby an increase by 1 dec for every 43 nm of reduction in d j occurs. This can be understood by the fact that the responsible defects originate mainly at the SiGe-Si interface. The perimeter current density shows for certain process splits an exponential dependence on the total thickness of the epitaxial layer t SiGe , with an increase by a decade for every 50 nm increase in thickness. Also, the generation and recombination lifetimes have been studied in order to determine an effective energy level of the electrically active defects.