Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs

Abstract

Heat removal technologies are among the most critical needs for 3D integration of high-performance microprocessors. As high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current, integrating high performance chips in a 3D stack greatly exacerbates challenges in power delivery and cooling of chips within the stack.This paper reports the configuration of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for 3D architectures with integrated high-performance processors in the 3D stack. The researchers demonstrate the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. The on-chip integrated microchannel heat sinks enable cooling of >100W/cm 2 of each high power density chip. A key element in this platform is the ability to assemble chips with electrical and fluidic I/Os and seal fluidic interconnections at each strata interface. Three assembly and fluidic sealing techniques are discussed. Fabrication, assembly, and experimental results of the novel fluidic sealing technologies that enable the microfluidic network in the inter-layer liquid cooling 3D integration platform are also reported.

A numerical hydrodynamic and thermal characterization of an inter-strata liquid cooling solution for 3D ICs

“…Unlike the interlayer cooling of Brunschviler, the key element in this platform was its ability to assemble chips with electrical and fluidic I/Os and seal fluidic interconnections at each stratum interface. Further developments of the interstrata cooling concept were reported by King et al (2010) where on-chip integrated microchannel heat sinks achieved a cooling performance of [100 W/cm 2 of each high power density chip. These developments represent significant steps in silicon integration of liquid cooling where the coolant is being circulated through each strata carrying heat from hot to cool zones.…”

3D modeling and simulation of heat transfer for internal channel cooling of 3D-chip stacks

“…Conventional fan-driven, forced convection air cooling techniques are not suitable for high power (higher than 100 W/cm 2 ) heat dissipation from the 3-D packages [4]. New cooling techniques must be developed to dissipate high heat flux [3][4][5][6]. Recently, many studies have been devoted to new technologies capable for high-efficiency cooling of integrated Microsystems.…”

Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer

“…High-performance processors are projected to dissipate more than 100W/cm 2 . A stack of these processors cannot be cooled using conventional forced-air cooling [6]. Microfluidic cooling has been demonstrated as a promising cooling technology for high-performance chip stack [7] [8].…”

“…The main challenge is that microfluidic I/Os need to be fabricated and assembled along with electrical I/Os to form good electrical and fluidic interconnections. Solder-and polymer-based fluidic I/O technologies have been reported in [6]. Solder-based fluidic I/Os have the advantages of good hermeticity, low moisture absorption, flexibility of I/O height, reworkability and simultaneous fabrication with electrical I/Os.…”